RE: Re: [microblaze-uclinux] ml310 development board sram failure

[<elynum@xxxxxxx>]

Yes, I'm sorry I always make that mistake it's the DDR SDRAM

Basically I've tried to follow the directions on xilinx's website under the updated ucf and updated mhs on how to do a build not with the microblaze but powerpc.   The link is
http://www.xilinx.com/products/boards/ml310/current/reference_designs/base/ml310_base_design_creation.pdf

The MHS file already contains the first text update but the UCF file doesn't contain the phase shift.  There's more to do than these directions you have to actually connect the ports to the nets because if you don't this will fail synthesis because it can't find the ddr_dcm or system_dcm modules that the UCF references.  

Any help on this will be greatly appreciated!!!!

> From: "Simon George" <simon.george@xxxxxxxxxx>
> Date: 2006/01/13 Fri AM 10:23:44 EST
> To: <elynum@xxxxxxx>
> CC: <microblaze-uclinux@xxxxxxxxxxxxxx>, 
>    "Paul Hartke" <paul.hartke@xxxxxxxxxx>
> Subject: RE: Re: [microblaze-uclinux] ml310 development board sram failure
> 
> Hi
> 
>  
> 
> Can you please confirm it is the SDRAM rather than SRAM that is proving
> problematic for you? - Your email Subject states the latter!
> 
>  
> 
> Regards
> 
> Simon
> 
>  
> 
> ------------------------------------------------------------------------
> -----------------
> 
>          Simon George
> 
>  _       Embedded Processor Specialist (Northern Europe)
> 
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> 
> \ \      XILINX - Benchmark House, 203 Brooklands Road,
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> 
> -----Original Message-----
> From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
> [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of Paul
> Hartke
> Sent: 13 January 2006 03:05
> To: microblaze-uclinux@xxxxxxxxxxxxxx; elynum@xxxxxxx
> Cc: microblaze-uclinux@xxxxxxxxxxxxxx
> Subject: Re: Re: [microblaze-uclinux] ml310 development board sram
> failure
> 
>  
> 
> I didn't read your original post closely enough:
> 
> "Paul, I've tried to update my MHS with the updated UCF, of course I had
> 
> to go and add and edit the netlist after getting all of that done I got
> a
> 
> timing constraint error."
> 
>  
> 
> You shouldn't have changed anything else except add these two lines to
> the
> 
> UCF file.
> 
>  
> 
> Quoting elynum@xxxxxxx:
> 
> > Paul,
> 
> > 
> 
> > That didn't work still have the timing constraint error.
> 
> > >
> 
> > > From: Paul Hartke <phartke@xxxxxxxxxxxx>
> 
> > > Date: 2006/01/12 Thu PM 02:35:04 EST
> 
> > > To: microblaze-uclinux@xxxxxxxxxxxxxx,  elynum@xxxxxxx
> 
> > > CC: microblaze-uclinux@xxxxxxxxxxxxxx
> 
> > > Subject: Re: Re: [microblaze-uclinux] ml310 development board sram
> 
> > failure
> 
> > >
> 
> > > Try removing all the other additions except:
> 
> > > INST "ddr_dcm/ddr_dcm/DCM_INST"      CLKOUT_PHASE_SHIFT = "FIXED";
> 
> > > INST "ddr_dcm/ddr_dcm/DCM_INST"      PHASE_SHIFT = "72";
> 
> > >
> 
> > > Paul
> 
> > >
> 
> > > Quoting elynum@xxxxxxx:
> 
> > > > Paul, I've tried to update my MHS with the updated UCF, of course
> I
> 
> > had
> 
> > > > to go and add and edit the netlist after getting all of that done
> I
> 
> > got a
> 
> > > > timing constraint error.
> 
> > > >
> 
> > > > The error I got is included in the xflow.log file I've included.
> 
> > > >
> 
> > > > If you don't have a clue on what the error is that I'm getting
> 
> > > >
> 
> > > > I was wondering if you could send me your BSB and MHS and UCF
> files
> 
> > so I
> 
> > > > test the SRAM.
> 
> > > >
> 
> > > > Thanks,
> 
> > > > >
> 
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> 
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> 
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> 
>  
> 
>  
> 
> 
> 

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