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RE: [microblaze-uclinux] kernel won't boot

To: <microblaze-uclinux@xxxxxxxxxxxxxx>
Subject: RE: [microblaze-uclinux] kernel won't boot
From: "Steve Spano" <steve@xxxxxxxxxxxxx>
Date: Mon, 30 Jan 2006 20:39:45 -0500
Importance: Normal
In-reply-to: <43DE5323.9040109@xxxxxx>
Organization: FLE
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
Hi Aurash,

Not sure if this helps but - the memory mapping for all of the
components on the ML401 board is probably much different then the
defaults for the kernel. 

There is a way to export the memory mapping from the EDK took over to an
autoconfig.h file. I believe that autoconfig is the one the carries the
memory map info (i.e. where the RAM/etc is located in the address space)

This could be the issue.

When we first got ours up and running, we started with an ML401 board. I
used the binary image for the SP3-1500 board (built by NuHo) as a known
good image and had it running on the ML401 board. We did this by placing
our ram/etc at the exact same locations that NuHo used on the SP3. This
let us shake out the hardware/etc and then onto the fun task of building
the kernel.

Steve Spano
President, Finger Lakes Engineering
(V) 607-277-1614 x223
(F) 800-835-7164
(C) 607-342-1150
steve@xxxxxxxxxxxxx
www.fl-eng.com

-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of Daniel
Hurni
Sent: Monday, January 30, 2006 12:56 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] kernel won't boot

After the memory test passed, I compilled the kernel and downloaded it 
with dl.sh. Do I need to do anything else ? I have no output on minicom 
after the memory test.

Aurash wrote:

> did you start the kernel after download?
> any boot log? (from the terminal)
> Aurash
> Daniel Hurni wrote:
>
>> Hi
>>
>> I got a Xilinx ML401 board and followed the tutorial from Jason Wu. 
>> The memory test passes, but when I download the Kernel, it doesn't 
>> boot. Any help would be great. I attached my system.mhs, if you need 
>> any other Informations, let me know.
>>
>> Daniel Hurni
>>
>>
------------------------------------------------------------------------
>>
>> # 
>>
########################################################################
###### 
>>
>> # Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build 
>> EDK_H.12.5.1
>> # Thu Dec 22 14:43:48 2005
>> # Target Board:  Xilinx Virtex 4 ML401 Evaluation Platform Rev 1
>> # Family:     virtex4
>> # Device:     xc4vlx25
>> # Package:     ff668
>> # Speed Grade:     -10
>> # Processor: Microblaze
>> # System clock frequency: 66.666667 MHz
>> # Debug interface: On-Chip HW Debug Module
>> # Data Cache: 16 KB
>> # Instruction Cache: 16 KB
>> # On Chip Memory :   8 KB
>> # Total Off Chip Memory :  72 MB
>> # - DDR_SDRAM_32Mx32 =  64 MB
>> # - FLASH_2Mx32 =   8 MB
>> # 
>>
########################################################################
###### 
>>
>>
>>
>> PARAMETER VERSION = 2.1.0
>>
>>
>> PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = IN
>> PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_Clk, DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn, DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_Addr, VEC = [0:12], DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr, VEC = [0:1], DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_CASn, DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_CKE, DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_CSn, DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_RASn, DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_WEn, DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_DM, VEC = [0:1], DIR = OUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_DQS, VEC = [0:1], DIR = INOUT
>> PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin = 
>> fpga_0_DDR_SDRAM_64Mx32_DDR_DQ, VEC = [0:15], DIR = INOUT
>> PORT fpga_0_FLASH_2Mx32_Mem_A_pin = fpga_0_FLASH_2Mx32_Mem_A, VEC = 
>> [6:29], DIR = OUT
>> PORT fpga_0_FLASH_2Mx32_Mem_BEN_pin = fpga_0_FLASH_2Mx32_Mem_BEN, VEC

>> = [0:3], DIR = OUT
>> PORT fpga_0_FLASH_2Mx32_Mem_WEN_pin = fpga_0_FLASH_2Mx32_Mem_WEN, DIR

>> = OUT
>> PORT fpga_0_FLASH_2Mx32_Mem_DQ_pin = fpga_0_FLASH_2Mx32_Mem_DQ, VEC =

>> [0:31], DIR = INOUT
>> PORT fpga_0_FLASH_2Mx32_Mem_OEN_pin = fpga_0_FLASH_2Mx32_Mem_OEN, VEC

>> = [0:0], DIR = OUT
>> PORT fpga_0_FLASH_2Mx32_Mem_CE_pin = fpga_0_FLASH_2Mx32_Mem_CE, VEC =

>> [0:0], DIR = OUT
>> PORT fpga_0_FLASH_2Mx32_Mem_ADV_LDN_pin = 
>> fpga_0_FLASH_2Mx32_Mem_ADV_LDN, DIR = OUT
>> PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = IN
>> PORT sys_clk_pin = dcm_clk_s, DIR = IN, SIGIS = DCMCLK
>> PORT sys_rst_pin = sys_rst_s, DIR = IN
>>
>>
>> BEGIN microblaze
>> PARAMETER INSTANCE = microblaze_0
>> PARAMETER HW_VER = 4.00.a
>> PARAMETER C_DEBUG_ENABLED = 1
>> PARAMETER C_NUMBER_OF_PC_BRK = 2
>> PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
>> PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
>> PARAMETER C_USE_ICACHE = 1
>> PARAMETER C_CACHE_BYTE_SIZE = 16384
>> PARAMETER C_USE_DCACHE = 1
>> PARAMETER C_DCACHE_BYTE_SIZE = 16384
>> PARAMETER C_ICACHE_BASEADDR = 0x24000000
>> PARAMETER C_ICACHE_HIGHADDR = 0x27ffffff
>> PARAMETER C_ADDR_TAG_BITS = 12
>> PARAMETER C_DCACHE_BASEADDR = 0x24000000
>> PARAMETER C_DCACHE_HIGHADDR = 0x27ffffff
>> PARAMETER C_DCACHE_ADDR_TAG = 12
>> PARAMETER C_FSL_LINKS = 1
>> BUS_INTERFACE SFSL0 = dlink
>> BUS_INTERFACE DLMB = dlmb
>> BUS_INTERFACE ILMB = ilmb
>> BUS_INTERFACE DOPB = mb_opb
>> BUS_INTERFACE IOPB = mb_opb
>> PORT CLK = sys_clk_s
>> PORT Interrupt = Interrupt
>> PORT DBG_UPDATE = DBG_UPDATE_s
>> PORT DBG_TDO = DBG_TDO_s
>> PORT DBG_TDI = DBG_TDI_s
>> PORT DBG_REG_EN = DBG_REG_EN_s
>> PORT DBG_CLK = DBG_CLK_s
>> PORT DBG_CAPTURE = DBG_CAPTURE_s
>> END
>>
>> BEGIN opb_v20
>> PARAMETER INSTANCE = mb_opb
>> PARAMETER HW_VER = 1.10.c
>> PARAMETER C_EXT_RESET_HIGH = 0
>> PORT SYS_Rst = sys_rst_s
>> PORT OPB_Clk = sys_clk_s
>> END
>>
>> BEGIN opb_mdm
>> PARAMETER INSTANCE = debug_module
>> PARAMETER HW_VER = 2.01.a
>> PARAMETER C_MB_DBG_PORTS = 1
>> PARAMETER C_USE_UART = 0
>> PARAMETER C_UART_WIDTH = 8
>> PARAMETER C_BASEADDR = 0x41400000
>> PARAMETER C_HIGHADDR = 0x4140ffff
>> PARAMETER C_WRITE_FSL_PORTS = 1
>> BUS_INTERFACE MFSL0 = dlink
>> BUS_INTERFACE SOPB = mb_opb
>> PORT OPB_Clk = sys_clk_s
>> PORT DBG_UPDATE_0 = DBG_UPDATE_s
>> PORT DBG_TDO_0 = DBG_TDO_s
>> PORT DBG_TDI_0 = DBG_TDI_s
>> PORT DBG_REG_EN_0 = DBG_REG_EN_s
>> PORT DBG_CLK_0 = DBG_CLK_s
>> PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
>> PORT Interrupt = debug_module_Interrupt
>> END
>>
>> BEGIN lmb_v10
>> PARAMETER INSTANCE = ilmb
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_EXT_RESET_HIGH = 0
>> PORT SYS_Rst = sys_rst_s
>> PORT LMB_Clk = sys_clk_s
>> END
>>
>> BEGIN lmb_v10
>> PARAMETER INSTANCE = dlmb
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_EXT_RESET_HIGH = 0
>> PORT SYS_Rst = sys_rst_s
>> PORT LMB_Clk = sys_clk_s
>> END
>>
>> BEGIN lmb_bram_if_cntlr
>> PARAMETER INSTANCE = dlmb_cntlr
>> PARAMETER HW_VER = 1.00.b
>> PARAMETER C_BASEADDR = 0x00000000
>> PARAMETER C_HIGHADDR = 0x00001fff
>> BUS_INTERFACE SLMB = dlmb
>> BUS_INTERFACE BRAM_PORT = dlmb_port
>> END
>>
>> BEGIN lmb_bram_if_cntlr
>> PARAMETER INSTANCE = ilmb_cntlr
>> PARAMETER HW_VER = 1.00.b
>> PARAMETER C_BASEADDR = 0x00000000
>> PARAMETER C_HIGHADDR = 0x00001fff
>> BUS_INTERFACE SLMB = ilmb
>> BUS_INTERFACE BRAM_PORT = ilmb_port
>> END
>>
>> BEGIN bram_block
>> PARAMETER INSTANCE = lmb_bram
>> PARAMETER HW_VER = 1.00.a
>> BUS_INTERFACE PORTA = ilmb_port
>> BUS_INTERFACE PORTB = dlmb_port
>> END
>>
>> BEGIN opb_uartlite
>> PARAMETER INSTANCE = RS232_Uart
>> PARAMETER HW_VER = 1.00.b
>> PARAMETER C_BAUDRATE = 115200
>> PARAMETER C_DATA_BITS = 8
>> PARAMETER C_ODD_PARITY = 0
>> PARAMETER C_USE_PARITY = 0
>> PARAMETER C_CLK_FREQ = 66000000
>> PARAMETER C_BASEADDR = 0x40600000
>> PARAMETER C_HIGHADDR = 0x4060ffff
>> BUS_INTERFACE SOPB = mb_opb
>> PORT OPB_Clk = sys_clk_s
>> PORT TX = fpga_0_RS232_Uart_TX
>> PORT RX = fpga_0_RS232_Uart_RX
>> PORT Interrupt = RS232_Uart_Interrupt
>> END
>>
>> BEGIN opb_ddr
>> PARAMETER INSTANCE = DDR_SDRAM_64Mx32
>> PARAMETER HW_VER = 2.00.b
>> PARAMETER C_OPB_CLK_PERIOD_PS = 14999
>> PARAMETER C_DDR_ASYNC_SUPPORT = 0
>> PARAMETER C_REG_DIMM = 0
>> PARAMETER C_DDR_TMRD = 20000
>> PARAMETER C_DDR_TWR = 20000
>> PARAMETER C_DDR_TRAS = 60000
>> PARAMETER C_DDR_TRC = 90000
>> PARAMETER C_DDR_TRFC = 80000
>> PARAMETER C_DDR_TRCD = 30000
>> PARAMETER C_DDR_TRRD = 15000
>> PARAMETER C_DDR_TRP = 30000
>> PARAMETER C_DDR_TREFC = 70300000
>> PARAMETER C_DDR_TREFI = 7800000
>> PARAMETER C_DDR_AWIDTH = 13
>> PARAMETER C_DDR_COL_AWIDTH = 9
>> PARAMETER C_DDR_BANK_AWIDTH = 2
>> PARAMETER C_MEM0_BASEADDR = 0x24000000
>> PARAMETER C_MEM0_HIGHADDR = 0x27ffffff
>> BUS_INTERFACE SOPB = mb_opb
>> PORT OPB_Clk = sys_clk_s
>> PORT Device_Clk = sys_clk_s
>> PORT Device_Clk_n = sys_clk_n_s
>> PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
>> PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
>> PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
>> PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
>> PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM
>> PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
>> PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
>> PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
>> PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
>> PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
>> PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
>> PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
>> PORT DDR_Clk90_in = ddr_clk_90_s
>> PORT DDR_Clk90_in_n = ddr_clk_90_n_s
>> PORT Device_Clk90_in = clk_90_s
>> PORT Device_Clk90_in_n = clk_90_n_s
>> END
>>
>> BEGIN opb_emc
>> PARAMETER INSTANCE = FLASH_2Mx32
>> PARAMETER HW_VER = 2.00.a
>> PARAMETER C_OPB_CLK_PERIOD_PS = 14999
>> PARAMETER C_NUM_BANKS_MEM = 1
>> PARAMETER C_MAX_MEM_WIDTH = 32
>> PARAMETER C_MEM0_WIDTH = 32
>> PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
>> PARAMETER C_SYNCH_MEM_0 = 0
>> PARAMETER C_TCEDV_PS_MEM_0 = 110000
>> PARAMETER C_TWC_PS_MEM_0 = 55000
>> PARAMETER C_TAVDV_PS_MEM_0 = 110000
>> PARAMETER C_TWP_PS_MEM_0 = 55000
>> PARAMETER C_THZCE_PS_MEM_0 = 10000
>> PARAMETER C_TLZWE_PS_MEM_0 = 35000
>> PARAMETER C_MEM0_BASEADDR = 0x22000000
>> PARAMETER C_MEM0_HIGHADDR = 0x227fffff
>> BUS_INTERFACE SOPB = mb_opb
>> PORT OPB_Clk = sys_clk_s
>> PORT Mem_WEN = fpga_0_FLASH_2Mx32_Mem_WEN
>> PORT Mem_OEN = fpga_0_FLASH_2Mx32_Mem_OEN
>> PORT Mem_DQ = fpga_0_FLASH_2Mx32_Mem_DQ
>> PORT Mem_CE = fpga_0_FLASH_2Mx32_Mem_CE
>> PORT Mem_BEN = fpga_0_FLASH_2Mx32_Mem_BEN
>> PORT Mem_A = fpga_0_FLASH_2Mx32_Mem_A_split
>> PORT Mem_ADV_LDN = fpga_0_FLASH_2Mx32_Mem_ADV_LDN
>> END
>>
>> BEGIN opb_timer
>> PARAMETER INSTANCE = opb_timer_1
>> PARAMETER HW_VER = 1.00.b
>> PARAMETER C_COUNT_WIDTH = 32
>> PARAMETER C_ONE_TIMER_ONLY = 1
>> PARAMETER C_BASEADDR = 0x41c00000
>> PARAMETER C_HIGHADDR = 0x41c0ffff
>> BUS_INTERFACE SOPB = mb_opb
>> PORT OPB_Clk = sys_clk_s
>> PORT Interrupt = opb_timer_1_Interrupt
>> END
>>
>> BEGIN opb_intc
>> PARAMETER INSTANCE = opb_intc_0
>> PARAMETER HW_VER = 1.00.c
>> PARAMETER C_BASEADDR = 0x41200000
>> PARAMETER C_HIGHADDR = 0x4120ffff
>> BUS_INTERFACE SOPB = mb_opb
>> PORT Intr = debug_module_Interrupt & RS232_Uart_Interrupt & 
>> opb_timer_1_Interrupt
>> PORT Irq = Interrupt
>> END
>>
>> BEGIN util_bus_split
>> PARAMETER INSTANCE = FLASH_2Mx32_util_bus_split_0
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_SIZE_IN = 32
>> PARAMETER C_LEFT_POS = 6
>> PARAMETER C_SPLIT = 30
>> PORT Sig = fpga_0_FLASH_2Mx32_Mem_A_split
>> PORT Out1 = fpga_0_FLASH_2Mx32_Mem_A
>> END
>>
>> BEGIN util_vector_logic
>> PARAMETER INSTANCE = sysclk_inv
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_SIZE = 1
>> PARAMETER C_OPERATION = not
>> PORT Op1 = sys_clk_s
>> PORT Res = sys_clk_n_s
>> END
>>
>> BEGIN util_vector_logic
>> PARAMETER INSTANCE = clk90_inv
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_SIZE = 1
>> PARAMETER C_OPERATION = not
>> PORT Op1 = clk_90_s
>> PORT Res = clk_90_n_s
>> END
>>
>> BEGIN util_vector_logic
>> PARAMETER INSTANCE = ddr_clk90_inv
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_SIZE = 1
>> PARAMETER C_OPERATION = not
>> PORT Op1 = ddr_clk_90_s
>> PORT Res = ddr_clk_90_n_s
>> END
>>
>> BEGIN dcm_module
>> PARAMETER INSTANCE = dcm_0
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_CLK0_BUF = TRUE
>> PARAMETER C_CLKDV_BUF = TRUE
>> PARAMETER C_CLKDV_DIVIDE = 1.500000
>> PARAMETER C_CLKIN_PERIOD = 10.000000
>> PARAMETER C_CLK_FEEDBACK = 1X
>> PARAMETER C_EXT_RESET_HIGH = 1
>> PORT CLKDV = sys_clk_s
>> PORT RST = net_gnd
>> PORT CLKIN = dcm_clk_s
>> PORT LOCKED = dcm_0_lock
>> PORT CLK0 = dcm_0_FB
>> PORT CLKFB = dcm_0_FB
>> END
>>
>> BEGIN dcm_module
>> PARAMETER INSTANCE = dcm_1
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_CLK0_BUF = TRUE
>> PARAMETER C_CLK90_BUF = TRUE
>> PARAMETER C_CLKIN_PERIOD = 15.000000
>> PARAMETER C_CLK_FEEDBACK = 1X
>> PARAMETER C_EXT_RESET_HIGH = 0
>> PORT CLKIN = sys_clk_s
>> PORT LOCKED = dcm_1_lock
>> PORT CLK0 = dcm_1_FB
>> PORT CLKFB = dcm_1_FB
>> PORT RST = dcm_0_lock
>> PORT CLK90 = clk_90_s
>> END
>>
>> BEGIN dcm_module
>> PARAMETER INSTANCE = dcm_2
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_CLK0_BUF = TRUE
>> PARAMETER C_CLK90_BUF = TRUE
>> PARAMETER C_CLKIN_PERIOD = 15.000000
>> PARAMETER C_CLK_FEEDBACK = 1X
>> PARAMETER C_PHASE_SHIFT = 19
>> PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
>> PARAMETER C_EXT_RESET_HIGH = 0
>> PORT CLKIN = ddr_feedback_s
>> PORT CLK90 = ddr_clk_90_s
>> PORT LOCKED = dcm_2_lock
>> PORT CLK0 = dcm_2_FB
>> PORT CLKFB = dcm_2_FB
>> PORT RST = dcm_1_lock
>> END
>>
>> BEGIN fsl_v20
>> PARAMETER INSTANCE = dlink
>> PARAMETER HW_VER = 2.00.a
>> PARAMETER C_EXT_RESET_HIGH = 0
>> PORT SYS_Rst = sys_rst_s
>> PORT FSL_Clk = sys_clk_s
>> END
>>
>>  
>>
>
>
> ___________________________
> microblaze-uclinux mailing list
> microblaze-uclinux@xxxxxxxxxxxxxx
> Project Home Page :
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> Mailing List Archive : 
> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>

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