[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [microblaze-uclinux] FSL_M_FULL
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi Adrian,
An easy way to get a VHDL/Verilog example is via the create/import
peripheral wizard in the EDK. It will create a basic FSL attached
adder that you can check out. I created my read and write macros
using Handel-C, so I'm not sure how useful the outputted verilog
would be to you.
Here's the EDK generated example module:
- --------------------------
////////////////////////////////////////////////////////////////////////
////////
//
//
// Definition of Ports
// FSL_Clk : Synchronous clock
// FSL_Rst : System reset, should always come from FSL bus
// FSL_S_Clk : Slave asynchronous clock
// FSL_S_Read : Read signal, requiring next available input to
be read
// FSL_S_Data : Input data
// FSL_S_Control : Control Bit, indicating the input data are
control word
// FSL_S_Exists : Data Exist Bit, indicating data exist in the
input FSL bus
// FSL_M_Clk : Master asynchronous clock
// FSL_M_Write : Write signal, enabling writing to output FSL bus
// FSL_M_Data : Output data
// FSL_M_Control : Control Bit, indicating the output data are
contol word
// FSL_M_Full : Full Bit, indicating output FSL bus is full
//
////////////////////////////////////////////////////////////////////////
////////
//----------------------------------------
// Module Section
//----------------------------------------
module myadder2
(
// ADD USER PORTS BELOW THIS LINE
// -- USER ports added here
// ADD USER PORTS ABOVE THIS LINE
// DO NOT EDIT BELOW THIS LINE ////////////////////
// Bus protocol ports, do not add or delete.
FSL_Clk,
FSL_Rst,
FSL_S_Clk,
FSL_S_Read,
FSL_S_Data,
FSL_S_Control,
FSL_S_Exists,
FSL_M_Clk,
FSL_M_Write,
FSL_M_Data,
FSL_M_Control,
FSL_M_Full
// DO NOT EDIT ABOVE THIS LINE ////////////////////
);
// ADD USER PORTS BELOW THIS LINE
// -- USER ports added here
// ADD USER PORTS ABOVE THIS LINE
input FSL_Clk;
input FSL_Rst;
output FSL_S_Clk;
output FSL_S_Read;
input [0 : 31] FSL_S_Data;
input FSL_S_Control;
input FSL_S_Exists;
output FSL_M_Clk;
output FSL_M_Write;
output [0 : 31] FSL_M_Data;
output FSL_M_Control;
input FSL_M_Full;
// ADD USER PARAMETERS BELOW THIS LINE
// --USER parameters added here
// ADD USER PARAMETERS ABOVE THIS LINE
//----------------------------------------
// Implementation Section
//----------------------------------------
// In this section, we povide an example implementation of MODULE
myadder2
// that does the following:
//
// 1. Read all inputs
// 2. Add each input to the contents of register 'sum' which
// acts as an accumulator
// 3. After all the inputs have been read, write out the
// content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS
times
//
// You will need to modify this example for
// MODULE myadder2 to implement your coprocessor
// Total number of input data.
localparam NUMBER_OF_INPUT_WORDS = 8;
// Total number of output data
localparam NUMBER_OF_OUTPUT_WORDS = 8;
// Define the states of state machine
localparam Idle = 3'b100;
localparam Read_Inputs = 3'b010;
localparam Write_Outputs = 3'b001;
reg [0:2] state;
// Accumulator to hold sum of inputs read at any point in time
reg [0:31] sum;
// Counters to store the number inputs read & outputs written
reg [0:NUMBER_OF_INPUT_WORDS - 1] nr_of_reads;
reg [0:NUMBER_OF_OUTPUT_WORDS - 1] nr_of_writes;
// CAUTION:
// The sequence in which data are read in should be
// consistant with the sequence they are written in the
// driver's myadder2.c file
assign FSL_S_Read = (state == Read_Inputs) ? FSL_S_Exists : 0;
assign FSL_M_Write = (state == Write_Outputs) ? ~FSL_M_Full : 0;
assign FSL_M_Data = sum;
always @(posedge FSL_Clk)
begin // process The_SW_accelerator
if (FSL_Rst) // Synchronous reset (active high)
begin
// CAUTION: make sure your reset polarity is consistant
with the
// system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
sum <= 0;
end
else
case (state)
Idle:
if (FSL_S_Exists == 1)
begin
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
sum <= 0;
end
Read_Inputs:
if (FSL_S_Exists == 1)
begin
// Coprocessor function (Adding) happens here
sum <= sum + FSL_S_Data;
if (nr_of_reads == 0)
begin
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
end
else
nr_of_reads <= nr_of_reads - 1;
end
Write_Outputs:
if (nr_of_writes == 0)
state <= Idle;
else
if (FSL_M_Full == 0) nr_of_writes <= nr_of_writes - 1;
endcase
end
endmodule
- -----------------------------
On Jan 31, 2006, at 8:29 PM, Adrian Wee Chin Mun wrote:
Hi John/Jonathan,
Or, do you mean that if the FIFO ever fills, even after MicroBlaze
reads
some data out, your core never recovers?
That appears to be the case. Once the FIFO fills and FSL_M_FULL
asserts, my hardware core never recovers. Last night I spent some time
modifying the FSL Master interface on my core to use more relaxed
timing but
it is still not working.
I think getting a prior working implementation might be a good idea
since I implemented mine solely based on the datasheets. Perhaps
you guys
can recommend an available implementation that is simple to observe
the
functionality? That would be helpful :)
Thanks
Adrian
-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of John
Williams
Sent: Wednesday, 1 February 2006 9:00 AM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] FSL_M_FULL
Hi Adrian,
Adrian Wee Chin Mun wrote:
I am working on hardware linked to the microblaze with FSL ports.
The FSL Slave interface on my hardware seems to be working fine
and the
FSL
Master interface also works in most cases. However, I seem to be
facing a
problem when the buffer on the FSL slave interface on the
microblaze gets
filled up.
[SNIP]
Which is a non BRAM implementation with a 16x32 buffer. Everything
works
fine as long as the buffer on the microblaze FSL slave is not full.
However
once it is full, it seems to hang my hardware. I have designed the
hardware
to mimic exactly the response from the datasheet (handles
FSL_M_FULL) and
I
have tested it for many cases by asserting the FSL_M_FULL with
ModelSim
and
it behaves predictably on simulation. However it doesn't seem to
work on
the
FPGA.
Isn't this the intended behaviour? Once the FSL buffer fills
(FSM_M_FULL asserted), then the master must block until the slave
(MicroBlaze in your case) reads from the other end.
Or, do you mean that if the FIFO ever fills, even after MicroBlaze
reads
some data out, your core never recovers?
I vaguely recall some discussion once that the FSL timing diagrams in
the microblaze reference guide are not strictly correct. So, you
might
have correctly implemented an incorrect specification. For the FSL
peripherals I've made before, I've always taken an existing working
one,
used that to get the FSL front end interfaces, then put my logic in
behind. Maybe you can try the same.
Also, I think the XPS Peripheral import wizard supports FSL these
days,
might be another approach to try.
Regards,
John
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-
uclinux
Mailing List Archive :
http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-
uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/
microblaze-uclinux/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.1 (Darwin)
iD8DBQFD4HvO4kOt3FHegqgRAo1qAJ9cD/hnDbqJosPjiGOiR8E1yk6KpgCcCKsQ
UdyT51yzwKIFeoEDi7QMeus=
=KIwM
-----END PGP SIGNATURE-----
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/