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RE: [microblaze-uclinux] DDR + XUP problem



I feel Xilinx DDR core has been quite stable now. You might have got the low
level timing wrong. Can you do the following check?

1. Google the part number of the memory chip on your DIMM module, and then
get its datasheet;

2. With the DDR DRAM datasheet, you can finger out the layout of your DIMM
module;

3. Get the OPB_DDR datasheet from the EDK;

4. Check the parameters in the EDK setting up page for the OPB_DDR core.
These parameters include the low level timing, width of data addresses and
bank address, memory banks, and etc.

5. Note that the DIMM has 64bit data bus. Make sure you get the latest
library package from Xilinx website, as there is the correct system.ucf file
for the DDR connection.

6. Make sure the clock has been connected properly. Have a look at a working
system.mhs for reference;

7. make sure you reset the system properly.

BTW, I don't trust their TestApp_Memory. It's too simple. I used to fill all
the memory with serial numbers, and then check its correctness, in case
overlap might happen.

Cheers

David

-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of leo han
Sent: 09 February 2006 01:22
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] DDR + XUP problem

I have a big C program (800KB) which must use DDR memory. I tried to use a 
256M ddr memory  with PPC and map all the sections to the DDR memory space 
except the boot and boot0.  However, the program can not start from DDR. The

problem occurs for microblaze also.
It almost kills me:(
Could anyone have any solution? Thanks.

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