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[microblaze-uclinux] Lost of data
Hi
I have some problems with uClinux running in my custom board. I have compile and launch the kernel and it seems to works correctly. But some times uClinux freezes. The kernel boots from a 8MB sdram memory (SDRAM_2Mx32 in the MHS show at the end of this message). When I try to load a simple kernel module for a char device I get:
#cd tmp
# lrz
.# waiting to receive.**B0100000023be50
#
# insmod ./hello.o
Using ./hello.o
I was assigned major number 254. To talk to
the driver, create a dev file with
'mknod /dev/hello c 254 0'.
Try various minor numbers. Try to cat and echo to
the device file.
Remove the device file and module when done.
# mknod ./hello c 254 0
# echo hi > hello
I already told you 0 times Hello world!
# ls
hello hello.o
# cat hello
cat: not found
# ps
ps: not found
#
Before load the module:
# ls bin
[ cp hello ln mknod reboot touch
agetty date hostname login modprobe rm true
basename dd ifconfig lrz mount rmmod uname
busybox echo init ls mv sh uptime
cat false insmod lsmod passwd shutdown version
chmod free kill lsz ps telnetd vi
cmp hd killall mkdir pwd test wget
And after load the module:
# ls /bin
echo init mount
Why I get lost of data??...is it any problem in the microblaze architecture?...maybe cache memory?...here is my MHS:
PARAMETER VERSION = 2.1.0
PORT fpga_0_W_R_Enable_GPIO_d_out_pin = fpga_0_W_R_Enable_GPIO_d_out, VEC = [0:1], DIR = OUT
PORT fpga_0_flash_2Mx8_Mem_A_pin = fpga_0_flash_2Mx8_Mem_A, VEC = [0:20], DIR = OUT
PORT fpga_0_flash_2Mx8_Mem_DQ_pin = fpga_0_flash_2Mx8_Mem_DQ, VEC = [0:7], DIR = INOUT
PORT fpga_0_flash_2Mx8_Mem_CEN_pin = fpga_0_flash_2Mx8_Mem_CEN, DIR = OUT
PORT fpga_0_flash_2Mx8_Mem_OEN_pin = fpga_0_flash_2Mx8_Mem_OEN, DIR = OUT
PORT fpga_0_flash_2Mx8_Mem_WEN_pin = fpga_0_flash_2Mx8_Mem_WEN, DIR = OUT
PORT fpga_0_flash_2Mx8_Mem_RPN_pin = fpga_0_flash_2Mx8_Mem_RPN, DIR = OUT
PORT fpga_0_jtag_reconfig_GPIO_d_out_pin = fpga_0_jtag_reconfig_GPIO_d_out, VEC = [0:3], DIR = OUT
PORT fpga_0_UART_RX_pin = fpga_0_UART_RX, DIR = IN
PORT fpga_0_UART_TX_pin = fpga_0_UART_TX, DIR = OUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_DQ_pin = fpga_0_SDRAM_2Mx32_SDRAM_DQ, VEC = [0:31], DIR = INOUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_Addr_pin = fpga_0_SDRAM_2Mx32_SDRAM_Addr, VEC = [0:10], DIR = OUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_BankAddr_pin = fpga_0_SDRAM_2Mx32_SDRAM_BankAddr, VEC = [0:1], DIR = OUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_Clk_pin = fpga_0_SDRAM_2Mx32_SDRAM_Clk, DIR = OUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_CKE_pin = fpga_0_SDRAM_2Mx32_SDRAM_CKE, DIR = OUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_CSn_pin = fpga_0_SDRAM_2Mx32_SDRAM_CSn, DIR = OUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_RASn_pin = fpga_0_SDRAM_2Mx32_SDRAM_RASn, DIR = OUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_CASn_pin = fpga_0_SDRAM_2Mx32_SDRAM_CASn, DIR = OUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_WEn_pin = fpga_0_SDRAM_2Mx32_SDRAM_WEn, DIR = OUT
PORT fpga_0_SDRAM_2Mx32_SDRAM_DQM_pin = fpga_0_SDRAM_2Mx32_SDRAM_DQM, VEC = [0:3], DIR = OUT
PORT sys_clk_pin = sys_clk_s, DIR = IN, SIGIS = CLK
PORT sys_rst_pin = sys_rst_s, DIR = IN
BEGIN opb_timer
PARAMETER INSTANCE = opb_timer_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 0
PARAMETER C_BASEADDR = 0x80200000
PARAMETER C_HIGHADDR = 0x8020ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = opb_timer_1_Interrupt
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER =
1.00.c
PARAMETER C_BASEADDR = 0x80100000
PARAMETER C_HIGHADDR = 0x8010ffff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = UART_Interrupt & opb_timer_1_Interrupt
END
# BEGIN bram_block
# PARAMETER INSTANCE = opb_bram_if_cntlr_1_bram
# PARAMETER HW_VER = 1.00.a
# BUS_INTERFACE PORTA = opb_bram_if_cntlr_1_port
# END
# BEGIN opb_bram_if_cntlr
# PARAMETER INSTANCE = opb_bram_if_cntlr_1
# PARAMETER HW_VER = 1.00.a
# PARAMETER c_opb_clk_period_ps = 40000
# PARAMETER c_baseaddr = 0x00000000
# PARAMETER c_highaddr = 0x00001fff
# BUS_INTERFACE SOPB = mb_opb
# BUS_INTERFACE PORTA = opb_bram_if_cntlr_1_port
# PORT OPB_Clk = sys_clk_s
# END
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 4096
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 4096
PARAMETER C_ICACHE_BASEADDR = 0x80800000
PARAMETER C_ICACHE_HIGHADDR = 0x80ffffff
# 23 - 14
PARAMETER C_ADDR_TAG_BITS = 11
PARAMETER C_DCACHE_BASEADDR = 0x80800000
PARAMETER C_DCACHE_HIGHADDR = 0x80ffffff
PARAMETER C_DCACHE_ADDR_TAG = 11
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT Interrupt = Interrupt
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_gpio
PARAMETER INSTANCE = jtag_reconfig
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_BASEADDR = 0x80700000
PARAMETER C_HIGHADDR = 0x8070ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT GPIO_d_out = fpga_0_jtag_reconfig_GPIO_d_out
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN util_bus_split
PARAMETER INSTANCE = flash_2Mx8_util_bus_split_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 0
# 21
PARAMETER C_SPLIT = 11
PORT Sig = Mem_A_split
PORT Out2 = fpga_0_flash_2Mx8_Mem_A
END
BEGIN opb_emc
PARAMETER INSTANCE = flash_2Mx8
PARAMETER HW_VER = 2.00.a
PARAMETER C_OPB_CLK_PERIOD_PS = 40000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_MEM0_WIDTH = 8
PARAMETER C_MAX_MEM_WIDTH = 8
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
# ******************************************
PARAMETER C_FAMILY = spartan3
PARAMETER C_TCEDV_PS_MEM_0 = 80000
PARAMETER C_TAVDV_PS_MEM_0 = 80000
PARAMETER C_THZCE_PS_MEM_0 = 25000
PARAMETER C_THZOE_PS_MEM_0 = 25000
PARAMETER C_TWC_PS_MEM_0 = 100000
PARAMETER C_TWP_PS_MEM_0 = 100000
PARAMETER C_TLZWE_PS_MEM_0 = 200000
PARAMETER C_MEM0_BASEADDR = 0x80400000
PARAMETER C_MEM0_HIGHADDR = 0x805fffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Mem_A = Mem_A_split
PORT Mem_DQ = fpga_0_flash_2Mx8_Mem_DQ
PORT Mem_CEN = fpga_0_flash_2Mx8_Mem_CEN
PORT Mem_OEN = fpga_0_flash_2Mx8_Mem_OEN
PORT Mem_WEN = fpga_0_flash_2Mx8_Mem_WEN
PORT Mem_RPN = fpga_0_flash_2Mx8_Mem_RPN
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x80310000
PARAMETER C_HIGHADDR = 0x8031ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
# #####################################################
BEGIN opb_gpio
PARAMETER INSTANCE = W_R_Enable
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 2
PARAMETER C_IS_DUAL = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_BASEADDR = 0x80080000
PARAMETER C_HIGHADDR = 0x8008ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT GPIO_d_out = fpga_0_W_R_Enable_GPIO_d_out
END
BEGIN opb_uartlite
PARAMETER INSTANCE = UART
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 25000000
PARAMETER C_BASEADDR = 0x80290000
PARAMETER C_HIGHADDR = 0x8029ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = UART_Interrupt
PORT RX = fpga_0_UART_RX
PORT TX = fpga_0_UART_TX
END
BEGIN opb_sdram
PARAMETER INSTANCE = SDRAM_2Mx32
PARAMETER HW_VER = 1.00.e
# PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0
PARAMETER C_OPB_CLK_PERIOD_PS = 40000
PARAMETER C_INCLUDE_BURST_SUPPORT = 1
PARAMETER C_SDRAM_CAS_LAT = 2
PARAMETER C_SDRAM_DWIDTH = 32
PARAMETER C_SDRAM_TCCD = 1
PARAMETER C_SDRAM_TRAS = 50000
PARAMETER C_SDRAM_TRC = 100000
PARAMETER C_SDRAM_TRFC = 100000
PARAMETER C_SDRAM_TRCD = 20000
PARAMETER C_SDRAM_TRRD = 20000
PARAMETER C_SDRAM_TRP = 20000
PARAMETER C_SDRAM_TREF = 64
PARAMETER C_SDRAM_AWIDTH = 11
PARAMETER C_SDRAM_COL_AWIDTH = 8
PARAMETER C_SDRAM_BANK_AWIDTH = 2
PARAMETER C_BASEADDR = 0x80800000
PARAMETER C_HIGHADDR = 0x80ffffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT SDRAM_CLK_in = sys_clk_s
PORT SDRAM_DQ = fpga_0_SDRAM_2Mx32_SDRAM_DQ
PORT SDRAM_Addr = fpga_0_SDRAM_2Mx32_SDRAM_Addr
PORT SDRAM_DQM = fpga_0_SDRAM_2Mx32_SDRAM_DQM
PORT SDRAM_WEn = fpga_0_SDRAM_2Mx32_SDRAM_WEn
PORT SDRAM_CKE = fpga_0_SDRAM_2Mx32_SDRAM_CKE
PORT SDRAM_CSn = fpga_0_SDRAM_2Mx32_SDRAM_CSn
PORT SDRAM_CASn = fpga_0_SDRAM_2Mx32_SDRAM_CASn
PORT SDRAM_RASn = fpga_0_SDRAM_2Mx32_SDRAM_RASn
PORT SDRAM_Clk = fpga_0_SDRAM_2Mx32_SDRAM_Clk
PORT SDRAM_BankAddr = fpga_0_SDRAM_2Mx32_SDRAM_BankAddr
END
# #####################################################
Regards,
Oscar