[microblaze-uclinux] ML310 DDR Timing

[Nob Kladjarern <nob.gatech@xxxxxxxxx>]

Hello,

I am a student trying to get the ML310 board to work properly. I am
actually using the PPC, not Microblaze, but since this seems to be the
most active forum, I'm hoping someone here would be able to help me out
please. I'm really new at this, so I'm not exactly sure what's going on.

I'm using EDK7.1SP2 right now. I know there's a problem with the DDR on
the ML310 board that has to be fixed by pasting in some lines from the
Xilinx Web site to the ucf and mhs files. But when I did that I got
errors when trying to regenerate the bitstream from the section of the
new lines under Answer Record #19385 saying can't find the module or
something along that line. Can someone please tell me what I have to
change to get this to work?

I also know there's an application note on finding the optimal DCM
phase shift. What I don't understand is what do I do once I build the
application as instructed and found out the optimal phase shift? Do I
use the clocks_0 module provided with the application note as my DCM
from this point on, with the phase shift fixed as per what I found?
Also, in which file am I supposed to put the 2 lines below?

// synthesis attribute CLKOUT_PHASE_SHIFT of dcm1 is "FIXED"
// synthesis attribute PHASE_SHIFT of dcm1 is "42"

Lastly, if I do perform this step to find out the optimal phase shift,
does it mean I no longer need those lines I pasted into the ucf file
that caused errors?

Thank you very much for any help anyone can offer. Like I said, I'm
really new at this. So sorry if some of my questions sound stupid. I
really appreciate any advice.

Sincerely,

Nob Kladjarern