Hi,I'm having a trouble compling designs in EDK for the ML401 board, even when using the reference designs provided by Xilinx. This has been an recurring problem for me. ( Reference design used is http://www.xilinx.com/products/boards/ml401/files/ml401_emb_ref_71.zip)
The error occurs whenever I attempt to use the DRAM or the ethernet modules. All up it throws about 7 errors which can be described in short as (full report can be seen in the zip file).
"plb_ddr_0_wrapper_async_fifo_v4_0 could not be resolved." "opb_ethernet_0_wrapper_async_fifo_v6_0 could not be resolved."Originally when I was learning the board I managed to get rid of the error after a few tries at reinstalling EDK and ISE. The problem came back later, but as I wasn't using the DRAM or the ethernet in my designs at the time I removed those modules and was able to ignore the problem.
However, now I need to use the ethernet module. After I tried a few things, I reinstalled EDK and ISE again. My design compiled so it seemed I had resolved the problem somehow. When I made another copy of my project with minor changes and attempted to compile that and it no longer worked. I went back to the design that had earlier compiled, made clean and compiled it again and it no longer worked too.
I would appreciate if someone could help me solve this problem I seem to be having. I'm fairly sure it has something to do the installation of my ISE or EDK. With some of my earlier tests projects that compile on other people's computers fail when I compile them on my own computer. It's driving me crazy.
Most of my attempts at solving this problem have been with EDK 7.1.02i and ISE 7.1.04i. The specifications of my computer are... AMD athlon 64bit 3500+ 960MB of RAM. Windows XP Professional Version 2002 Service Pack 2
(not running 64 bit windows). John Xue
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