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RE: [microblaze-uclinux] a question about opb bus

To: <microblaze-uclinux@xxxxxxxxxxxxxx>
Subject: RE: [microblaze-uclinux] a question about opb bus
From: "Steve Spano" <steve@xxxxxxxxxxxxx>
Date: Wed, 8 Mar 2006 07:07:34 -0500
Importance: Normal
In-reply-to: <BAY23-F1AD4C9361E1B59F9B5D17D2EF0@xxxxxxx>
Organization: FLE
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
Hi Leo,

Whats your application for the 6 microblazes? Is it research only?

Steve Spano
President, Finger Lakes Engineering
(V) 607-277-1614 x223
(F) 800-835-7164
(C) 607-342-1150
steve@xxxxxxxxxxxxx
www.fl-eng.com

-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of leo han
Sent: Tuesday, March 07, 2006 8:58 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] a question about opb bus

We have a design of 6 microblazes with opb bus and DDR memory. The 6 
microblazes are attached to the opb bus as masters. The ddr memory and 
another opb_bram are slaves. The data layout on DDR memory is like this:
    D_A: read only by microblaze 1;
    D_B: read  by microblaze 2, and write by microblaze 5;
These two segments are not overlapped.
I found a strange problem. When I disables all the writes from
microblaze 5, 
the system works. WHen I allow it to write memory, it could only run a 
little bit, then microblaze 1 will report a pipelin stall and abort.
When I slow down the microblaze 5's execution by adding some idle loops 
(like a loop for 50000 times), it works again. However, if you just run
the 
idle loop for 10000 times, it will fail.

I don't use any fancy opb features, even not using the dynamic priority.
I 
don't use any locks for the data memory. BTW, I am using XUP board with
EDK 
7.1.

Can anybody point out some possible problem with the design?

attached is the mhs file.

Thanks.



PARAMETER VERSION = 2.1.0


PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, VEC = [0:2],
DIR = 
OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, VEC = [0:2],
DIR = 
OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, VEC = [0:12],
DIR 
= OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, VEC =
[0:1], 
DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, VEC = [0:7], DIR
= 
OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, VEC = [0:7],
DIR = 
INOUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, VEC = [0:63],
DIR = 
INOUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT
PORT fpga_0_VGA_FrameBuffer_TFT_LCD_CLK = 
fpga_0_VGA_FrameBuffer_TFT_LCD_CLK, DIR = OUTPUT
PORT fpga_0_VGA_FrameBuffer_TFT_LCD_HSYNC_pin = 
fpga_0_VGA_FrameBuffer_TFT_LCD_HSYNC, DIR = OUTPUT
PORT fpga_0_VGA_FrameBuffer_TFT_LCD_VSYNC_pin = 
fpga_0_VGA_FrameBuffer_TFT_LCD_VSYNC, DIR = OUTPUT
PORT fpga_0_VGA_FrameBuffer_TFT_LCD_BLNK_pin = 
fpga_0_VGA_FrameBuffer_TFT_LCD_BLNK, DIR = OUTPUT
PORT fpga_0_VGA_FrameBuffer_TFT_LCD_B_pin = 
fpga_0_VGA_FrameBuffer_TFT_LCD_B, VEC = [5:0], DIR = OUTPUT
PORT fpga_0_VGA_FrameBuffer_TFT_LCD_G_pin = 
fpga_0_VGA_FrameBuffer_TFT_LCD_G, VEC = [5:0], DIR = OUTPUT
PORT fpga_0_VGA_FrameBuffer_TFT_LCD_R_pin = 
fpga_0_VGA_FrameBuffer_TFT_LCD_R, VEC = [5:0], DIR = OUTPUT
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
PORT sys_rst_pin = sys_rst_s, DIR = INPUT


BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_0
BUS_INTERFACE IPLB = plb
BUS_INTERFACE DPLB = plb
PORT PLBCLK = sys_clk_s
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT CPMC405CLOCK = proc_clk_s
END

BEGIN ppc405
PARAMETER INSTANCE = ppc405_1
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_1
END

BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_block
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Ext_Reset_In = sys_rst_s
PORT Slowest_sync_clk = sys_clk_s
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
PORT Core_Reset_Req = C405RSTCORERESETREQ
PORT System_Reset_Req = C405RSTSYSRESETREQ
PORT Rstc405resetchip = RSTC405RESETCHIP
PORT Rstc405resetcore = RSTC405RESETCORE
PORT Rstc405resetsys = RSTC405RESETSYS
PORT Bus_Struct_Reset = sys_bus_reset
PORT Dcm_locked = dcm_1_lock
END

BEGIN plb_v34
PARAMETER INSTANCE = plb
PARAMETER HW_VER = 1.02.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = sys_clk_s
END

BEGIN opb_v20
PARAMETER INSTANCE = opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT OPB_Clk = sys_clk_s
END

BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
PARAMETER HW_VER = 1.01.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_NUM_ADDR_RNG = 1
PARAMETER C_RNG0_BASEADDR = 0x00000000
PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE MOPB = opb
PORT PLB_Clk = sys_clk_s
PORT OPB_Clk = sys_clk_s
END

BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = opb
PORT OPB_Clk = sys_clk_s
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END

BEGIN opb_ddr
PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
PARAMETER HW_VER = 2.00.b
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CLK_PAIRS = 4
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_TMRD = 20000
PARAMETER C_DDR_TWR = 20000
PARAMETER C_DDR_TRAS = 60000
PARAMETER C_DDR_TRC = 90000
PARAMETER C_DDR_TRFC = 100000
PARAMETER C_DDR_TRCD = 30000
PARAMETER C_DDR_TRRD = 20000
PARAMETER C_DDR_TRP = 30000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 10
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_DDR_DWIDTH = 64
PARAMETER C_MEM0_BASEADDR = 0x30000000
PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
BUS_INTERFACE SOPB = opb
PORT OPB_Clk = sys_clk_s
PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
PORT DDR_BankAddr = 
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk &

ddr_clk_feedback_out_s
PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn
& 
0b0
PORT Device_Clk90_in = clk_90_s
PORT Device_Clk90_in_n = clk_90_n_s
PORT Device_Clk = sys_clk_s
PORT Device_Clk_n = sys_clk_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN plb_tft_cntlr_ref
PARAMETER INSTANCE = VGA_FrameBuffer
PARAMETER HW_VER = 1.00.d
PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0b00110111111
PARAMETER C_PIXCLK_IS_BUSCLK_DIVBY4 = 0b1
BUS_INTERFACE MPLB = plb
PORT TFT_LCD_CLK = fpga_0_VGA_FrameBuffer_TFT_LCD_CLK
PORT TFT_LCD_HSYNC = fpga_0_VGA_FrameBuffer_TFT_LCD_HSYNC
PORT TFT_LCD_VSYNC = fpga_0_VGA_FrameBuffer_TFT_LCD_VSYNC
PORT TFT_LCD_B = fpga_0_VGA_FrameBuffer_TFT_LCD_B
PORT TFT_LCD_G = fpga_0_VGA_FrameBuffer_TFT_LCD_G
PORT TFT_LCD_R = fpga_0_VGA_FrameBuffer_TFT_LCD_R
PORT TFT_LCD_BLNK = fpga_0_VGA_FrameBuffer_TFT_LCD_BLNK
END

BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_plb_clk_period_ps = 10000
PARAMETER c_baseaddr = 0xffff0000
PARAMETER c_highaddr = 0xffff3fff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
PORT PLB_Clk = sys_clk_s
END

BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN util_vector_logic
PARAMETER INSTANCE = sysclk_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = sys_clk_s
PORT Res = sys_clk_n_s
END

BEGIN util_vector_logic
PARAMETER INSTANCE = clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = clk_90_s
PORT Res = clk_90_n_s
END

BEGIN util_vector_logic
PARAMETER INSTANCE = ddr_clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_clk_90_s
PORT Res = ddr_clk_90_n_s
END

BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKFX_BUF = TRUE
PARAMETER C_CLKFX_DIVIDE = 1
PARAMETER C_CLKFX_MULTIPLY = 3
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLK90 = clk_90_s
PORT CLKFX = proc_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_PHASE_SHIFT = 60
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK0 = dcm_1_FB
PORT CLKFB = dcm_1_FB
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
PARAMETER C_FSL_LINKS = 5
PARAMETER C_USE_BARREL = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = opb
BUS_INTERFACE IOPB = opb
BUS_INTERFACE MFSL0 = fsl_0_1
BUS_INTERFACE MFSL1 = fsl_0_2
BUS_INTERFACE MFSL2 = fsl_0_3
BUS_INTERFACE MFSL3 = fsl_0_4
BUS_INTERFACE MFSL4 = fsl_0_5
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
END

BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = opb
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00020000
PARAMETER C_HIGHADDR = 0x00027fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_ibram
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEMSIZE = 65536
BUS_INTERFACE PORTA = ilmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = lmv_databram
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEMSIZE = 65536
BUS_INTERFACE PORTA = dlmb_port
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_1
PARAMETER HW_VER = 4.00.a
PARAMETER C_FSL_LINKS = 1
BUS_INTERFACE DLMB = dlmb_1
BUS_INTERFACE ILMB = ilmb_1
BUS_INTERFACE DOPB = opb
BUS_INTERFACE IOPB = opb
BUS_INTERFACE SFSL0 = fsl_0_1
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb_1
BUS_INTERFACE BRAM_PORT = dlmb_port1
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb_1
BUS_INTERFACE BRAM_PORT = ilmb_port1
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_1
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port1
BUS_INTERFACE PORTB = dlmb_port1
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_2
PARAMETER HW_VER = 4.00.a
PARAMETER C_FSL_LINKS = 2
BUS_INTERFACE DLMB = dlmb_2
BUS_INTERFACE ILMB = ilmb_2
BUS_INTERFACE DOPB = opb
BUS_INTERFACE IOPB = opb
BUS_INTERFACE MFSL0 = fsl_2_4
BUS_INTERFACE SFSL0 = fsl_0_2
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr_2
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb_2
BUS_INTERFACE BRAM_PORT = dlmb_port2
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr_2
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb_2
BUS_INTERFACE BRAM_PORT = ilmb_port2
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_2
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port2
BUS_INTERFACE PORTB = dlmb_port2
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb_2
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb_2
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_3
PARAMETER HW_VER = 4.00.a
PARAMETER C_FSL_LINKS = 2
BUS_INTERFACE DLMB = dlmb_3
BUS_INTERFACE ILMB = ilmb_3
BUS_INTERFACE DOPB = opb
BUS_INTERFACE IOPB = opb
BUS_INTERFACE MFSL0 = fsl_3_4
BUS_INTERFACE SFSL0 = fsl_0_3
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr_3
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = dlmb_3
BUS_INTERFACE BRAM_PORT = dlmb_port3
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr_3
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = ilmb_3
BUS_INTERFACE BRAM_PORT = ilmb_port3
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_3
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port3
BUS_INTERFACE PORTB = dlmb_port3
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb_3
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb_3
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_4
PARAMETER HW_VER = 4.00.a
PARAMETER C_FSL_LINKS = 3
BUS_INTERFACE DLMB = dlmb_4
BUS_INTERFACE ILMB = ilmb_4
BUS_INTERFACE DOPB = opb
BUS_INTERFACE IOPB = opb
BUS_INTERFACE MFSL0 = fsl_4_5
BUS_INTERFACE SFSL0 = fsl_0_4
BUS_INTERFACE SFSL1 = fsl_2_4
BUS_INTERFACE SFSL2 = fsl_3_4
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr_4
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb_4
BUS_INTERFACE BRAM_PORT = dlmb_port4
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr_4
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb_4
BUS_INTERFACE BRAM_PORT = ilmb_port4
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_4
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port4
BUS_INTERFACE PORTB = dlmb_port4
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb_4
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb_4
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_5
PARAMETER HW_VER = 4.00.a
PARAMETER C_FSL_LINKS = 2
BUS_INTERFACE DLMB = dlmb_5
BUS_INTERFACE ILMB = ilmb_5
BUS_INTERFACE DOPB = opb
BUS_INTERFACE IOPB = opb
BUS_INTERFACE SFSL0 = fsl_4_5
BUS_INTERFACE SFSL1 = fsl_0_5
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr_5
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = dlmb_5
BUS_INTERFACE BRAM_PORT = dlmb_port5
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr_5
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = ilmb_5
BUS_INTERFACE BRAM_PORT = ilmb_port5
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_5
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port5
BUS_INTERFACE PORTB = dlmb_port5
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb_5
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb_5
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_0_1
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 32
PARAMETER C_FSL_DEPTH = 16
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_0_2
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 32
PARAMETER C_FSL_DEPTH = 16
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_0_3
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 32
PARAMETER C_FSL_DEPTH = 64
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_0_4
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 32
PARAMETER C_FSL_DEPTH = 16
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_0_5
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 32
PARAMETER C_FSL_DEPTH = 16
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_2_4
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 32
PARAMETER C_FSL_DEPTH = 64
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_3_4
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 32
PARAMETER C_FSL_DEPTH = 64
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_4_5
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 32
PARAMETER C_FSL_DEPTH = 128
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END

BEGIN bram_block
PARAMETER INSTANCE = bram_YUV
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = YUV_bram
END

BEGIN opb_bram_if_cntlr
PARAMETER INSTANCE = opb_bram_YUV
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x50000000
PARAMETER C_HIGHADDR = 0x50007fff
BUS_INTERFACE SOPB = opb
BUS_INTERFACE PORTA = YUV_bram
END

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References:
- [microblaze-uclinux] a question about opb bus
  - From: leo han
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