[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [microblaze-uclinux] a question about opb bus
This design has a lot of masters on the opb bus which must put a lot of
timing pressure on it. Out of curiousity, how long does the design take to
implement? I'd double check the timing analysis results--*.par and *.twr
files--to make sure timing is actually met.
Might also be worth running a full memory test from each Microblaze into the
DDR. That would stress the system which would be useful to make sure the
kinks are really worked out before you run your application. The uclinux
design zip file for the XUPV2P board has a memory test that covers more
than just the standard BSB test.
Quoting leo han <wenwenti@xxxxxxxxxxx>:
> I did a small experiment today. When I disable processor 5 and add some
> write operations to other processors, the system can still work. So it
> that the bus is not saturated.
> I don't have any idea now.
microblaze-uclinux mailing list
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/