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[microblaze-uclinux] Microblaze4 slow kernel download with XMD
Hi,
finally I got EDK8.1 and I tried to convert my Spartan3 design from
EDK7.1 with Microblaze3 + sdram
to EDK8.1 with Microblaze4 + MCH sdram controller.
The problem is XMD takes a very long time to download the kernel image,
although I connected FSL
for fast download as with old Microblaze3 design.
I use dl.sh script for download, and xilinx parallel cable IV in
compatibility mode (cable III mode) in Linux.
The download time was 1min with Mb3 design versus 4min with Mb4 design!
It seems the FSL fast download
doesn't work.
Do anyone has ever experimented this problem? Any tips?
After download the kernel boots and works fine.
Here is XMD log and my system.mhs file.
# time ./dl.sh
Kimage is /tftpboot/image.bin
Xilinx Microprocessor Debug (XMD) Engine
Xilinx EDK 8.1.01 Build EDK_I.19.5
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
XMD%
Loading MHS File..
Processor(s) in System ::
Microblaze(1) : microblaze_0
Address Map for Processor microblaze_0
(0x00000000-0x00001fff) dlmb_cntlr dlmb
(0x00000000-0x00001fff) ilmb_cntlr ilmb
(0x40600000-0x4060ffff) console_uart mb_opb
(0x41200000-0x4120ffff) system_intc mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41c00000-0x41c0ffff) system_timer mb_opb
(0x80000000-0x81ffffff) sdram_controller mb_opb
(0x80000000-0x81ffffff) sdram_controller ixcl
(0x80000000-0x81ffffff) sdram_controller dxcl
Reusing 780200E4 key.
Reusing FC0200E4 key.
Connecting to cable (Parallel Port - parport0).
WinDriver v7.01 Jungo (c) 1997 - 2005 Build Date: Aug 10 2005 X86 32bit
16:24:42.
parport0: baseAddress=0x378, ecpAddress=0x778
LPT base address = 0378h.
ECP base address = 0778h.
ECP hardware is detected.
Cable connection established.
Connecting to cable (Parallel Port - parport0) in ECP mode.
WARNING:iMPACT - Module xpc4drvr is not loaded. Please reinstall the cable
drivers. See Answer Record 18612.
Cable connection failed.
Connecting to cable (Parallel Port - parport0).
WinDriver v7.01 Jungo (c) 1997 - 2005 Build Date: Aug 10 2005 X86 32bit
16:24:42.
LPT base address = 0378h.
ECP base address = 0778h.
Cable connection established.
ECP port test failed. Using download cable in compatibility mode.
JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 05045093 8 XCF02S
2 0141c093 6 XC3S400
Assuming, Device No: 2 contains the MicroBlaze system
Connected to the JTAG MicroProcessor Debug Module (MDM)
No of processors = 1
MicroBlaze Processor 1 Configuration :
-------------------------------------
Version............................4.00.a
No of PC Breakpoints...............2
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........on
Instruction Cache Base Address.....0x80000000
Instruction Cache High Address.....0x81ffffff
Data Cache Support.................on
Data Cache Base Address............0x80000000
Data Cache High Address............0x81ffffff
Exceptions Support................off
FPU Support.......................off
FSL DCache Support.................on
FSL ICache Support.................on
Hard Divider Support...............on
Hard Multiplier Support............on
Barrel Shifter Support.............on
MSR clr/set Instruction Support....on
Compare Instruction Support........off
Number of FSL ports..............1
MBsfsl(0)-MDMmfsl(0) Connected..........Yes
JTAG MDM Connected to MicroBlaze 1
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234
Processor started. Type "stop" to stop processor
Closing MDM communication with Processor 1
real 4m5.909s
user 0m5.734s
sys 3m59.666s
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.1.01 Build EDK_I.19.5
# Tue Mar 7 18:00:15 2006
# Target Board: Custom
# Family: spartan3
# Device: xc3s400
# Package: pq208
# Speed Grade: -4
# Processor: Microblaze
# System clock frequency: 53.333333 MHz
# Debug interface: On-Chip HW Debug Module
# Data Cache: 8 KB
# Instruction Cache: 2 KB
# On Chip Memory : 8 KB
# Total Off Chip Memory : 32 MB
# - Generic_SDRAM = 32 MB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT sys_clk_pin = vfast_clk_pin, DIR = I, SIGIS = DCMCLK
PORT sys_rst_pin = ext_rst, DIR = I
PORT opbsdram_clkfb = opbsdram_clkfb, DIR = I, SIGIS = DCMCLK
PORT opbsdram_ck = opbsdram_clk, DIR = O
PORT opbsdram_cke = opbsdram_cke, DIR = O
PORT opbsdram_cs = opbsdram_cs, DIR = O
PORT opbsdram_ras = opbsdram_ras, DIR = O
PORT opbsdram_cas = opbsdram_cas, DIR = O
PORT opbsdram_we = opbsdram_we, DIR = O
PORT opbsdram_dqm = opbsdram_dqm, VEC = [0:1], DIR = O
PORT opbsdram_baddr = opbsdram_baddr, VEC = [0:1], DIR = O
PORT opbsdram_addr = opbsdram_addr, VEC = [0:12], DIR = O
PORT opbsdram_dq = opbsdram_dq, VEC = [0:15], DIR = IO
PORT console_uart_RX_pin = console_uart_rx, DIR = I
PORT console_uart_TX_pin = console_uart_tx, DIR = O
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 2048
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 8192
PARAMETER C_ICACHE_USE_FSL = 1
PARAMETER C_DCACHE_USE_FSL = 1
PARAMETER C_ICACHE_BASEADDR = 0x80000000
PARAMETER C_ICACHE_HIGHADDR = 0x81ffffff
PARAMETER C_DCACHE_BASEADDR = 0x80000000
PARAMETER C_DCACHE_HIGHADDR = 0x81ffffff
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_DIV = 1
PARAMETER C_USE_MSR_INSTR = 1
PARAMETER C_FSL_LINKS = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
BUS_INTERFACE IXCL = ixcl
BUS_INTERFACE DXCL = dxcl
BUS_INTERFACE SFSL0 = download_link
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT Interrupt = Interrupt
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 0
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
PARAMETER C_WRITE_FSL_PORTS = 1
BUS_INTERFACE SOPB = mb_opb
BUS_INTERFACE MFSL0 = download_link
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN mch_opb_sdram
PARAMETER INSTANCE = sdram_controller
PARAMETER HW_VER = 1.00.a
PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
PARAMETER C_INCLUDE_OPB_BURST_SUPPORT = 0
PARAMETER C_SDRAM_AWIDTH = 13
PARAMETER C_SDRAM_BANK_AWIDTH = 2
PARAMETER C_SDRAM_COL_AWIDTH = 9
PARAMETER C_SDRAM_DWIDTH = 16
PARAMETER C_SDRAM_TMRD = 2
PARAMETER C_SDRAM_TCCD = 1
PARAMETER C_SDRAM_TRAS = 45000
PARAMETER C_SDRAM_TRC = 66000
PARAMETER C_SDRAM_TRFC = 75000
PARAMETER C_SDRAM_TRCD = 20000
PARAMETER C_SDRAM_TRRD = 15000
PARAMETER C_SDRAM_TRP = 20000
PARAMETER C_SDRAM_TREF = 64
PARAMETER C_SDRAM_CAS_LAT = 3
PARAMETER C_MCH_OPB_CLK_PERIOD_PS = 18750
PARAMETER C_MEM0_BASEADDR = 0x80000000
PARAMETER C_MEM0_HIGHADDR = 0x81ffffff
BUS_INTERFACE SOPB = mb_opb
BUS_INTERFACE MCH0 = ixcl
BUS_INTERFACE MCH1 = dxcl
PORT SDRAM_CLK_in = opbsdram_clk_out
PORT SDRAM_DQ = opbsdram_dq
PORT SDRAM_Addr = opbsdram_addr
PORT SDRAM_DQM = opbsdram_dqm
PORT SDRAM_WEn = opbsdram_we
PORT SDRAM_CKE = opbsdram_cke
PORT SDRAM_CSn = opbsdram_cs
PORT SDRAM_CASn = opbsdram_cas
PORT SDRAM_RASn = opbsdram_ras
PORT SDRAM_Clk = opbsdram_clk
PORT SDRAM_BankAddr = opbsdram_baddr
PORT MCH_OPB_Clk = sys_clk_s
END
BEGIN opb_timer
PARAMETER INSTANCE = system_timer
PARAMETER HW_VER = 1.00.b
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x41c00000
PARAMETER C_HIGHADDR = 0x41c0ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = timer_interrupt
END
BEGIN opb_intc
PARAMETER INSTANCE = system_intc
PARAMETER HW_VER = 1.00.c
PARAMETER C_HAS_IPR = 0
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = console_uart_interrupt & timer_interrupt
PORT OPB_Clk = sys_clk_s
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_vintfb
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 12.50000
PARAMETER C_CLKDV_DIVIDE = 1.5
PARAMETER C_CLKDV_BUF = TRUE
PARAMETER C_CLKIN_BUF = TRUE
PORT RST = net_gnd
PORT CLKIN = vfast_clk_pin
PORT CLKFB = vfast_clk
PORT CLK0 = vfast_clk
PORT CLKDV = sys_clk_s
END
BEGIN opb_uartlite
PARAMETER INSTANCE = console_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 53_452_800
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = console_uart_interrupt
PORT RX = console_uart_rx
PORT TX = console_uart_tx
PORT OPB_Clk = sys_clk_s
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_extfb
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_CLKIN_PERIOD = 18.75000
PARAMETER C_CLK0_BUF = FALSE
PARAMETER C_CLKFB_BUF = TRUE
PARAMETER C_CLKIN_BUF = FALSE
PORT RST = net_gnd
PORT CLKIN = sys_clk_s
PORT CLKFB = opbsdram_clkfb
PORT CLK0 = opbsdram_clk_out
PORT LOCKED = sextfb_locked
END
BEGIN util_reduced_logic
PARAMETER INSTANCE = util_logic_rstgen
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 2
PORT Op1 = sextfb_locked & ext_rst
PORT Res = sys_rst_s
END
BEGIN fsl_v20
PARAMETER INSTANCE = download_link
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END