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Re: [microblaze-uclinux] kernel builded don't boot - almost ...

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] kernel builded don't boot - almost ...
From: <adimbox-uclinux@xxxxxxxxxxxx>
Date: Tue, 14 Mar 2006 20:37:12 -0300 (ART)
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Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
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Well, I'm not sure what was wrong ... the thing is, I got the uClinux source again and recompiled the kernel, and now it boot. Almost ... it is crashing, stoping at the login - doesn't fulfill the line, as shown below. I've supressed all the Flash stuff from the kernel, since I'm not using it now (I'm working just with RAM) ... but I guess it wouldn't make so much difference, right ?

Below is a copy of the boot log :

Linux version 2.4.32-uc0 (adi_mohr@ibiza) (gcc version 3.4.1 ( Xilinx EDK 8.1 Build EDK_I.17 121005 )) #6 Tue Mar 14 20:17:15 UTC 2006
On node 0 totalpages: 65536
zone(0): 65536 pa
zone(1): 0 pages.
zone(2): 0 pages.
CPU: MICROBLAZE             &nbs! p;
Kerserial on UARTLite
Calibrating delay loop... 49.76 BogoMIPS
Memory: 256MB = 256MB total
Memory: 257020KB available (1210K code, 1080K data, 52K init)
Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
Inode cache hash table entries: 16384 (order: 5, 131072 bytes)
Mount cache hash table entrieuffer cache hash table entries: 16384 (order: 4, 65536 bytes)
Page-! cache hash table entries: 65536 (order: 6, 262144 bytes)
POSIX conformance testing by UNI
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initoblaze UARTlite serial driver version 1.00
ttyS0 at 0x40600000 (irq = 2) is a Microblaze UARTlite
Starting kswapd
xgpio #0 at 0x40020000 mapped to 0x40020000
xgpio #1 at 0x40000000 mapped to 0x40000000
Xilinx GPIO registered
RAMDISK driver initiae 1024 blocksize                                     eth0: using sgDMA mode.
eth0: Xilinx EMAC #0 at 0x40C00000 mapped to 0x40C00000, irq=1
eth0: id 2.0h; block id 7, type 1
uclinux[mtd]: RAM probe address=0x3016809c size=0xd5000
uclinux[mtd]: root filesystem index=0
NET4: Linux TCs: ICMP, UDP, TCP
IP: routing ! cache hash table of 2048 buckets, 16Kbytes
TCP: Hash tables configured (established 16384 bind 32768)
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
VFS: Mounted root (romfs filesystem) readonly.
Freeing init memory: 52K
Mounting proc:
Mounting var:
Populating /var:
Running local start scripts.
Mounting /etc/config:
Populating /etc/config:
flatfsd: Nonexistent or bad flatfs (-48), creating new one...
flatfsd: Failed to write flatfs (-48): No such device
flatfsd: Created 3 configuration files (142 bytes)
Setting hostname:
Setting up interface lo:
Starting DHCP client:
Starting thttpd:
eth0: Link carrier lost.

uclinux-auto lo

adimbox-uclinux@xxxxxxxxxxxx escreveu:

Hello people !

I've finally built my on kernel :) but it do! n't boot ... I'm using a Xilinx Virtex2 Pro.

The thing is :
- the binary from the Microblaze's page (uclinux-xupv2p_rev_1_1) works fine, so it isn't some mistake in the download ...
- using the auto-conf.in found at uclinux-xupv2p_rev_1_1, I made a new binary, which works fine too
- using my on auto-con.in, I can compile the kernel, it generates the binary, but it don't boot - the terminal stays blank

What I'm doing :
- I build the plataform, which generates the auto-conf.in (in project\microblaze_0\libsrc\uclinux_v1_00_a)
- then, I copy it to Linux, in uClinux-2.4.x\arch\microblaze\plataform\uclinux-auto
- then I 'make' the kernel, which will generate the binary
- finally, I download it with XMD :
dow -data image.bin 0x30000000
mwr 0x100 0
rwr 5 0x100
rwr pc 0x30000000
con

Am! I missing something ? When I do that with auto-conf.in from uclinux-xupv2p_! rev_1_1, everything works, but when I use my on auto-conf.in, it dosn't boot ... Which uClinux version should I use in XPS (a, b, c or d?, in uclinux-xupv2p_rev_1_1 is 'a', does it matter using other? )

Follow my auto-conf.in - the only differences I've found was about the cache, which I'm using and the original has not :

############################################################
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
# Description: uClinux Configuration File
#
############################################################

# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x30000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x10000000

# LMB_MEMORY Settings
define_hex CONFIG_XILINX_LMB_START 0x00000000
define_hex CONFIG_XILINX_L! MB_SIZE 0x00002000

# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 100000000

# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex2p
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_FPU 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_E! XCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x30000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1 def! ine_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 14
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 16384
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 0
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x30000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 14
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 16384
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 4.00.a

# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHA! DDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x50000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b

# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x50000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b

# Definitions for MDM_0
define_! ! string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x41400000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x4140FFFF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY virtex2p
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 1
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a

# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_Uart_1
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x40600000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x4060FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 100000000
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 9600
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_Uart_1
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 2

# Definitions for ETHERNET_0
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
define_int CONFIG_XILINX_ETHERNET_0_DEV_BLK_ID 1
define_int CONFIG_XILINX_ETHERNET_0_DEV_MIR_ENABLE 1
define_hex CONFIG_XILINX_ETHERNET_0_BASEADDR 0x40C00000
define_hex CONFIG_XILINX_ETHERNET_0_HIGHADDR 0x40C0FFFF
define_int CONFIG_XILINX_ETHERNET_0_RESET_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_INTR_COALESCE 1
define_int CONFIG_XILINX_ETHERNET_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS 10000
define_string CONFIG_XILINX_ETHERNET_0_FAMILY virtex2p
define_int CONFIG_XILINX_ETHERNET_0_IPIF_RDFIFO_DEPTH 32768
define_int CONFIG_XILINX_ETHERNET_0_IPIF_WRFIFO_DEPTH 32768
define_hex CONFIG_XILINX_ETHERNET_0_MIIM_CLKDVD 0x0000001F
define_int CONFIG_XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_PAD_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_FCS_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_DEPTH 64
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_BRAM_1_SRL_0 0
define_int CONFIG_XILINX_ETHERNET_0_HALF_DUPLEX_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_ERR_COUNT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_CAM_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_CAM_BRAM_0_SRL_1 1
define_int CONFIG_XILINX_ETHERNET_0_JUMBO_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_MII_EXIST 1
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
define_string CONFIG_XILINX_ETHERNET_0_HW_VER 1.02.a
define_int CONFIG_XILINX_ETHERNET_0_IRQ 1

# Definitions for GPIO_0
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x40020000
define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x4002FFFF
define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_0_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 4
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 0
define_hex CONFIG_XILINX_GPIO_0_DOUT! ! _DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b

# Definitions for GPIO_1
define_string CONFIG_XILINX_GPIO_1_INSTANCE DIPSWs_4Bit
define_hex CONFIG_XILINX_GPIO_1_BASEADDR 0x40040000
define_hex CONFIG_XILINX_GPIO_1_HIGHADDR 0x4004FFFF
define_int CONFIG_XILINX_GPIO_1_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_1_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_1_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_1_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_1_GPIO_WIDTH 4
define_int CONFIG_XILINX_GPIO_1_ALL_INPUTS ! 1
defi! ne_int CONFIG_XILINX_GPIO_1_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_1_IS_BIDIR 1
define_hex CONFIG_XILINX_GPIO_1_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_1_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_1_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_1_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_1_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_1_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_1_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_1_INSTANCE DIPSWs_4Bit
define_string CONFIG_XILINX_GPIO_1_HW_VER 3.01.b

# Definitions for GPIO_2
define_string CONFIG_XILINX_GPIO_2_INSTANCE PushButtons_5Bit
define_hex CONFIG_XILINX_GPIO_2_BASEADDR 0x40000000
define_hex CONFIG_XILINX_GPIO_2_HIGHADDR 0x4000FFFF
define_int CONFIG_XILINX_GPIO_2_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_2_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_2_OPB_DWIDTH 32 define_string CONFIG_XILINX_GPIO_2_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_2_GPIO_WIDTH 5
define_int CONFIG_XILINX_GPIO_2_ALL_INPUTS 1
define_int CONFIG_XILINX_GPIO_2_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_2_IS_BIDIR 1
define_hex CONFIG_XILINX_GPIO_2_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_2_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_2_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_2_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_2_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_2_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_2_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_2_INSTANCE PushButtons_5Bit
define_string CONFIG_XILINX_GPIO_2_HW_VER 3.01.b

# Definitions for DDR_0
define_string CONFIG_XILINX_DDR_0_INSTANCE DDR_256MB_32MX64_rank1_row13_col10_cl2_5
define_int CONFIG_XILINX_DDR_0_DDR_ASYNSUPPORT 0
define_int CONFIG_XILINX_DDR_0_INCLUDE_BURST_SUP! PORT 0
define_int CONFIG_XILINX_DDR_0_REG_DIMM 0
define_int CONFIG_XILINX_DDR_0_EXTRA_TSU 0
define_int CONFIG_XILINX_DDR_0_NUM_BANKS_MEM 1
define_int CONFIG_XILINX_DDR_0_NUM_CLK_PAIRS 4
define_string CONFIG_XILINX_DDR_0_FAMILY virtex2p
define_int CONFIG_XILINX_DDR_0_DDR_TMRD 20000
define_int CONFIG_XILINX_DDR_0_DDR_TWR 20000
define_int CONFIG_XILINX_DDR_0_DDR_TWTR 1
define_int CONFIG_XILINX_DDR_0_DDR_TRAS 60000
define_int CONFIG_XILINX_DDR_0_DDR_TRC 90000
define_int CONFIG_XILINX_DDR_0_DDR_TRFC 100000
define_int CONFIG_XILINX_DDR_0_DDR_TRCD 30000
define_int CONFIG_XILINX_DDR_0_DDR_TRRD 20000
define_int CONFIG_XILINX_DDR_0_DDR_TREFC 70300000
define_int CONFIG_XILINX_DDR_0_DDR_TREFI 7800000
define_int CONFIG_XILINX_DDR_0_DDR_TRP 30000
define_int CONFIG_XILINX_DDR_0_DDR_CAS_LAT 2
define_int CONFIG_XILINX_DDR_0_DDR_DWIDTH 64
define_int CONFIG_XILINX_DDR_0_DDR_AWIDTH 13
define_int CONFIG_XILINX_DDR_0_DDR_COL_AWIDTH 10
define_int CONFIG_XILINX_DDR_0_DDR_BANK_AWIDTH 2
define_hex CONFIG_XILINX_DDR_0_MEM0_BASEADDR 0x30000000
define_hex CONFIG_XILINX_DDR_0_MEM0_HIGHADDR 0x3FFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM2_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM2_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM3_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM3_HIGHADDR 0x00000000
define_int CONFIG_XILINX_DDR_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_CLK_PERIOD_PS 10000
define_int CONFIG_XILINX_DDR_0_SIM_INIT_TIME_PS 200000000
define_string CONFIG_XILINX_DDR_0_INSTANCE DDR_256MB_32MX64_rank1_row13_col10_cl2_5
define_string CONFIG_XILINX_DDR_0_HW_VER 2.00.b

# Definitions for PS2_DUAL_REF_0!
define_string CONFIG_XILINX_PS2_DUAL_REF_0_INSTANCE PS2_Ports
define_string CONFIG_XILINX_PS2_DUAL_REF_0_BASEADDR 0x7a400000
define_string CONFIG_XILINX_PS2_DUAL_REF_0_HIGHADDR 0x7a40ffff
define_string CONFIG_XILINX_PS2_DUAL_REF_0_INSTANCE PS2_Ports
define_string CONFIG_XILINX_PS2_DUAL_REF_0_HW_VER 1.00.a

# Definitions for AC97_0
define_string CONFIG_XILINX_AC97_0_INSTANCE Audio_Codec
define_int CONFIG_XILINX_AC97_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_AC97_0_OPB_AWIDTH 32
define_hex CONFIG_XILINX_AC97_0_BASEADDR 0x7D400000
define_hex CONFIG_XILINX_AC97_0_HIGHADDR 0x7D40FFFF
define_int CONFIG_XILINX_AC97_0_PLAYBACK 1
define_int CONFIG_XILINX_AC97_0_RECORD 1
define_int CONFIG_XILINX_AC97_0_INTR_LEVEL 1
define_int CONFIG_XILINX_AC97_0_USE_BRAM 1
define_string CONFIG_XILINX_AC97_0_INSTANCE Audio_Codec
define_string CONFIG_XILINX_AC97_0_HW_VER 2.00.a

# Definitions for TIMER_0
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_FAMILY virtex2p
define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 1
define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x41C00000
define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x41C0FFFF
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
define_int CONFIG_XILINX_TIMER_0_IRQ 0

# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0 define_string CONFIG_XILINX_INTC_0_FAMILY virtex2p
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x41200000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x4120FFFF
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 3
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000004
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000004
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000003
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0!
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c

# P! eripheral counts
define_int CONFIG_XILINX_AC97_NUM_INSTANCES 1
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
define_int CONFIG_XILINX_PS2_DUAL_REF_NUM_INSTANCES 1
define_int CONFIG_XILINX_DDR_NUM_INSTANCES 1
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 3
define_int CONFIG_XILINX_ETHERNET_NUM_INSTANCES 1

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- [microblaze-uclinux] kernel builded don't boot
  - From: adimbox-uclinux

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