Re: [microblaze-uclinux] SMP

[George Smith <gesmith@xxxxxxxxxxxxxxxxxx>]

hi 
 I was meaning SMP in the classical sense, where multiple cpu's a
running symetrically under an OS. As far as master/slave MP, I
understand how to accomplish that and there's certainly application
there.

 The point on the the write allocates is that I believe you could do
your own cache coherency via CacheLink if the microblaze would do a
write allocate on write miss. The write allocate would stall the
processor and allow you to do you own work. (Of course it already does a
read allocate so that end is covered.)

 Of course it would also be nice to have a Load-Link/Store-Conditional
set of instructions for atomic ops...

gesmith
 


On Thu, 2006-03-16 at 19:32, Paul Hartke wrote:
> Hi George,
> 
> What is your definition of SMP?  Since Microblaze doesn't natively support
> hardware cache coherency, I don't think SMP is possible in the mainline
> sense of the term.  However, there are lots of folks doing multi-processor
> designs which are described throughout the archives.
> 
> Not sure I understand the point about write allocate on a miss...
> 
> Paul
> 
> Quoting George Smith <gesmith@xxxxxxxxxxxxxxxxxx>:
> > hi
> >  Is anyone working with microblaze as an SMP with uClinux? If so how are
> > you over coming the fact that the cache doesn't do a write allocate on
> > miss?
> >
> > gesmith
> > --
> > George Smith
> > VP Engineering
> > Linear Acoustic, Inc
> >
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-- 
George Smith
VP Engineering
Linear Acoustic, Inc

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