[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[microblaze-uclinux] SSL cannot allocate memory - how to free memory ?

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] SSL cannot allocate memory - how to free memory ?
From: "A. Arthur Mohr" <adimbox-uclinux@xxxxxxxxxxxx>
Date: Fri, 7 Apr 2006 21:02:29 -0300 (ART)
Domainkey-signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com.br; h=Message-ID:Received:Date:From:Reply-To:Subject:To:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=cngsEX2Wssku0bGLG0UbZ95B7QKlF+GzV22hP5yAut8Na4bkOwDrlrdlQR7mac1KCEB1kYpSYKHl+mn4C2KW5ooLZbFLE7aezq27k0qj0+y6yKPp45EeoKDDXSohJUOa2FY27henMtQsE2Sv8iEF9Dbl7UYwAeCjkZcUgj+vfhY= ;
In-reply-to: <20060407151256.I42650@xxxxxxxxxxxxxxxxxx>
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx

Hello again !

This is the deal : I finally have compiled SSH with Openssl :-)
I uploaded it to the board to test it, and it doesn't work.
Telnetd, ftpd, httpd, all god to go. But when I call ssh or openssl, it says it cant allocate any memory (as I understood). Here is the message (the same for ssh and openssl) :

# openssl
Allocation of length 1814732 from process 81 failed
Free pages:      250960kB (     0kB HighMem)
Zone:DMA freepages:250960kB
Zone:Normal freepages:     0kB
Zone:HighMem freepages:     0kB
( Active: 259, inactive: 81, free: 62740 )
0*4kB 0*8kB 1*1B 0*512kB 1*1024kB 122*2048kB = 250960kB)
= 0kB)
= 0kB)
Unable to allocate RAM for process text/data, errno 12
#

I do have all the memory (256 mb) allocated for the board, but I'm not sure how to allocate some of it as Linux memory, instead of Filesystem memory - if I am understanding the problem correctly.

Here is the system.mhs, if it helps. The board is a XUP V2P with 256mb RAM.

#
# ##############################################################################
#
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
#
# Thu Mar 23 21:14:15 2006
#
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
# Family:    virtex2p
# Device:    xc2vp30
# Package:    ff896
# Speed Grade:    -7
#
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# Data Cache: 16 KB
# Instruction Cache: 16 KB
# On Chip Memory :   8 KB
# Total Off Chip Memory : 256 MB
#   - DDR_SDRAM_32Mx64 Single Rank = 256 MB
#
# ##############################################################################

PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT
PORT fpga_0_Ethernet_MAC_slew1_pin = net_vcc, DIR = OUTPUT
PORT fpga_0_Ethernet_MAC_slew2_pin = net_vcc, DIR = OUTPUT
PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = OUTPUT
PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = INPUT
PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = INPUT
PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = OUTPUT, VEC = [3:0]
PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = OUTPUT
PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = INPUT
PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = OUTPUT
PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = INPUT
PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = INPUT
PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = INPUT
PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = INPUT, VEC = [3:0]
PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = INOUT
PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = INOUT
PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = INOUT, VEC = [0:3]
PORT fpga_0_PushButtons_5Bit_GPIO_IO_pin = fpga_0_PushButtons_5Bit_GPIO_IO, DIR = INOUT, VEC = [0:4]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, DIR = OUTPUT, VEC = [0:2]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, DIR = OUTPUT, VEC = [0:2]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, DIR = OUTPUT, VEC = [0:12]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, DIR = OUTPUT, VEC = [0:1]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, DIR = OUTPUT, VEC = [0:7]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, DIR = INOUT, VEC = [0:7]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, DIR = INOUT, VEC = [0:63]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT
PORT fpga_0_Audio_Codec_Bit_Clk_pin = fpga_0_Audio_Codec_Bit_Clk, DIR = INPUT
PORT fpga_0_Audio_Codec_AC97Reset_n_pin = fpga_0_Audio_Codec_AC97Reset_n, DIR = OUTPUT
PORT fpga_0_Audio_Codec_SData_In_pin = fpga_0_Audio_Codec_SData_In, DIR = INPUT
PORT fpga_0_Audio_Codec_SData_Out_pin = fpga_0_Audio_Codec_SData_Out, DIR = OUTPUT
PORT fpga_0_Audio_Codec_Sync_pin = fpga_0_Audio_Codec_Sync, DIR = OUTPUT
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
PORT sys_rst_pin = sys_rst_s, DIR = INPUT

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 16384
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 16384
PARAMETER C_ICACHE_BASEADDR = 0x30000000
PARAMETER C_ICACHE_HIGHADDR = 0x3fffffff
PARAMETER C_ADDR_TAG_BITS = 14
PARAMETER C_DCACHE_BASEADDR = 0x30000000
PARAMETER C_DCACHE_HIGHADDR = 0x3fffffff
PARAMETER C_DCACHE_ADDR_TAG = 14
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT Interrupt = Interrupt
END

BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = RS232_Uart_1_Interrupt
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END

BEGIN opb_ethernet
PARAMETER INSTANCE = Ethernet_MAC
PARAMETER HW_VER = 1.02.a
PARAMETER C_DMA_PRESENT = 1
PARAMETER C_IPIF_RDFIFO_DEPTH = 32768
PARAMETER C_IPIF_WRFIFO_DEPTH = 32768
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_BASEADDR = 0x40c00000
PARAMETER C_HIGHADDR = 0x40c0ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
END

BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_4Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x4002ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END

BEGIN opb_gpio
PARAMETER INSTANCE = PushButtons_5Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT IP2INTC_Irpt = PushButtons_5Bit_IP2INTC_Irpt
PORT GPIO_IO = fpga_0_PushButtons_5Bit_GPIO_IO
END

BEGIN opb_ddr
PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
PARAMETER HW_VER = 2.00.b
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CLK_PAIRS = 4
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_TMRD = 20000
PARAMETER C_DDR_TWR = 20000
PARAMETER C_DDR_TRAS = 60000
PARAMETER C_DDR_TRC = 90000
PARAMETER C_DDR_TRFC = 100000
PARAMETER C_DDR_TRCD = 30000
PARAMETER C_DDR_TRRD = 20000
PARAMETER C_DDR_TRP = 30000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 10
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_DDR_DWIDTH = 64
PARAMETER C_MEM0_BASEADDR = 0x30000000
PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
PORT Device_Clk90_in = clk_90_s
PORT Device_Clk90_in_n = clk_90_n_s
PORT Device_Clk = sys_clk_s
PORT Device_Clk_n = sys_clk_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN opb_ac97
PARAMETER INSTANCE = Audio_Codec
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x7d400000
PARAMETER C_HIGHADDR = 0x7d40ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = Audio_Codec_Interrupt
PORT Bit_Clk = fpga_0_Audio_Codec_Bit_Clk
PORT SData_In = fpga_0_Audio_Codec_SData_In
PORT SData_Out = fpga_0_Audio_Codec_SData_Out
PORT Sync = fpga_0_Audio_Codec_Sync
PORT AC97Reset_n = fpga_0_Audio_Codec_AC97Reset_n
END

BEGIN opb_timer
PARAMETER INSTANCE = opb_timer_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x41c00000
PARAMETER C_HIGHADDR = 0x41c0ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = opb_timer_1_Interrupt
END

BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = Audio_Codec_Interrupt & RS232_Uart_1_Interrupt & LEDs_4Bit_IP2INTC_Irpt & PushButtons_5Bit_IP2INTC_Irpt & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt
END

BEGIN util_vector_logic
PARAMETER INSTANCE = sysclk_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = sys_clk_s
PORT Res = sys_clk_n_s
END

BEGIN util_vector_logic
PARAMETER INSTANCE = clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = clk_90_s
PORT Res = clk_90_n_s
END

BEGIN util_vector_logic
PARAMETER INSTANCE = ddr_clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_clk_90_s
PORT Res = ddr_clk_90_n_s
END

BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLK90 = clk_90_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_PHASE_SHIFT = 60
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK0 = dcm_1_FB
PORT CLKFB = dcm_1_FB
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END

Abra sua conta no Yahoo! Mail - 1GB de espaço, alertas de e-mail no celular e anti-spam realmente eficaz.

Follow-Ups:
- Re: [microblaze-uclinux] SSL cannot allocate memory - how to free memory ?
  - From: John Williams

References:
- [microblaze-uclinux] Write to GPIO
  - From: Dag Mattis Pettersen

Prev by Date: Re: [microblaze-uclinux] SSH / LD Errors - can't compile ssl
Next by Date: [no subject]
Previous by thread: Re: [microblaze-uclinux] Write to GPIO
Next by thread: Re: [microblaze-uclinux] SSL cannot allocate memory - how to free memory ?
Index(es):
- Date
- Thread