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[microblaze-uclinux] systemace driver freezes linux

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] systemace driver freezes linux
From: Dries Schellekens <dries.schellekens@xxxxxxxxxxxxxxxx>
Date: Fri, 21 Apr 2006 18:32:36 +0200
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
User-agent: Thunderbird 1.5 (Windows/20051201)

Hey,

I am also experiencing problems with SystemAce on the XUP V2P board.

The SYSACE Self Test is successfull (see attachment #1).

However loading my design from a CompactFlash card fails. The SYSTEM ACEERROR LED blinks when no card is present, but when I insert the card theLED stays red and my design is not loaded.

If I enable the System Ace driver, Linux freezes completely (seedifference between boot log in attachment #2 and #3).

What could be wrong? I also added my configuration in attachment:system.{mss,mhs} and generated auto-config.in.



Cheers,

Dries


Disclaimer: http://www.kuleuven.be/cwis/email_disclaimer.htm

XUP-V2Pro BuiltIn Self Test Main Menu Rev. 1.5 June. 2005
----------------------------------------------------------
1 - Test SATA port with Aurora loopback.
2 - Test Ethernet with WEB example.
3 - Test AC97 audio codec.
4 - Test System ACE.
5 - Test DDR SDRAM.
6 - Test Expansion connectors.
q - Quit

SYSACE Self Test
----------------
Initalizing sysace...		done!
Querying device version...	done!
  Identified SYSACE version #4108
Querying formatted memory device...	SUCCESS!

  <Type q to return to menu>

XUP-V2Pro BuiltIn Self Test Main Menu Rev. 1.5 June. 2005
----------------------------------------------------------
1 - Test SATA port with Aurora loopback.
2 - Test Ethernet with WEB example.
3 - Test AC97 audio codec.
4 - Test System ACE.
5 - Test DDR SDRAM.
6 - Test Expansion connectors.
q - Quit

Goodbye.

Linux version 2.4.32-uc0 (dschelle@vierre) (gcc version 3.4.1 ( Xilinx EDK 8.1 Build EDK_I.17 121005 )) #50 Fri Apr 21 17:58:03 CEST 2006
On node 0 totalpages: 65536
zone(0): 65536 pages.
zone(1): 0 pages.
zone(2): 0 pages.
CPU: MICROBLAZE
Kernel command line: 
Console: xmbserial on UARTLite
Calibrating delay loop... 49.76 BogoMIPS
Memory: 256MB = 256MB total
Memory: 256916KB available (1106K code, 1287K data, 60K init)
Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
Inode cache hash table entries: 16384 (order: 5, 131072 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer cache hash table entries: 16384 (order: 4, 65536 bytes)
Page-cache hash table entries: 65536 (order: 6, 262144 bytes)
POSIX conformance testing by UNIFIX
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Microblaze UARTlite serial driver version 1.00
ttyS0 at 0x40600000 (irq = 3) is a Microblaze UARTlite
Starting kswapd
xgpio #0 at 0x40000000 mapped to 0x40000000
xgpio #1 at 0x40020000 mapped to 0x40020000
xgpio #2 at 0x40040000 mapped to 0x40040000
Xilinx GPIO registered
RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize
loop: loaded (max 8 devices)
eth0: using sgDMA mode.
eth0: Xilinx EMAC #0 at 0x40C00000 mapped to 0x40C00000, irq=1
eth0: id 2.0h; block id 7, type 1
uclinux[mtd]: RAM probe address=0x3015ab50 size=0x3010000
uclinux[mtd]: root filesystem index=0
Initializing Cryptographic API
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP
IP: routing cache hash table of 2048 buckets, 16Kbytes
TCP: Hash tables configured (established 16384 bind 32768)
Sending DHCP requests ., OK
IP-Config: Got DHCP answer from 192.168.0.1, my address is 192.168.0.126
IP-Config: Complete:
      device=eth0, addr=192.168.0.126, mask=255.255.255.0, gw=192.168.0.1,
     host=192.168.0.126, domain=esat.kuleuven.be, nis-domain=(none),
     bootserver=192.168.0.1, rootserver=192.168.0.1, rootpath=
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
VFS: Mounted root (cramfs filesystem) readonly.
Freeing init memory: 60K
Mounting proc: 
Mounting var: 
Populating /var: 
Running local start scripts.
Setting hostname: 
Setting up interface lo: 
Setting up interface eth0: 
Starting inetd: 
Starting thttpd: 

uclinux-auto login: root
Password: 
# cat /proc/cpuinfo
CPU-Family:	Microblaze
FPGA-Arch:	virtex2p
CPU-Ver:	4.00.a
CPU-MHz:   100.00
BogoMips:	49.76
HW-Div:         yes
HW-Shift:       yes
Icache:        64kB
Dcache:       64kB
HW-Debug:       yes
# mount
/dev/mtdblock0 on / type cramfs (ro)
/proc on /proc type proc (rw)
none on /var type ramfs (rw)
# init: /bin/syslogd respawning too fast

Linux version 2.4.32-uc0 (dschelle@vierre) (gcc version 3.4.1 ( Xilinx EDK 8.1 Build EDK_I.17 121005 )) #49 Fri Apr 21 17:36:28 CEST 2006
On node 0 totalpages: 65536
zone(0): 65536 pages.
zone(1): 0 pages.
zone(2): 0 pages.
CPU: MICROBLAZE
Kernel command line: 
Console: xmbserial on UARTLite
Calibrating delay loop... 49.76 BogoMIPS
Memory: 256MB = 256MB total
Memory: 256904KB available (1121K code, 1283K data, 60K init)
Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
Inode cache hash table entries: 16384 (order: 5, 131072 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer cache hash table entries: 16384 (order: 4, 65536 bytes)
Page-cache hash table entries: 65536 (order: 6, 262144 bytes)
POSIX conformance testing by UNIFIX
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Microblaze UARTlite serial driver version 1.00
ttyS0 at 0x40600000 (irq = 3) is a Microblaze UARTlite
Starting kswapd
xgpio #0 at 0x40000000 mapped to 0x40000000
xgpio #1 at 0x40020000 mapped to 0x40020000
xgpio #2 at 0x40040000 mapped to 0x40040000
Xilinx GPIO registered
RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize
loop: loaded (max 8 devices)
Initializing SystemAce driver

 PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = uclinux
 PARAMETER OS_VER = 1.00.d
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER lmb_memory = ilmb_cntlr
 PARAMETER main_memory_bank = 0
 PARAMETER main_memory = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
 PARAMETER stdin = RS232_Uart_1
 PARAMETER stdout = RS232_Uart_1
 PARAMETER TARGET_DIR = c:/users/dschelle/linux_mb/linux
 PARAMETER main_memory_size = 0x10000000
END


BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = microblaze_0
 PARAMETER COMPILER = mb-gcc
 PARAMETER ARCHIVER = mb-ar
 PARAMETER XMDSTUB_PERIPHERAL = debug_module
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = opbarb
 PARAMETER DRIVER_VER = 1.02.a
 PARAMETER HW_INSTANCE = mb_opb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = RS232_Uart_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = emac
 PARAMETER DRIVER_VER = 1.00.f
 PARAMETER HW_INSTANCE = Ethernet_MAC
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = sysace
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = SysACE_CompactFlash
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = LEDs_4Bit
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = DIPSWs_4Bit
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = PushButtons_5Bit
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = ddr
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = opb_timer_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = intc
 PARAMETER DRIVER_VER = 1.00.c
 PARAMETER HW_INSTANCE = opb_intc_0
END

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.1.01 Build EDK_I.19.5
# Fri Apr 21 17:28:00 2006
# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
# Family:	 virtex2p
# Device:	 xc2vp30
# Package:	 ff896
# Speed Grade:	 -7
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# Data Cache: 64 KB
# Instruction Cache: 64 KB
# On Chip Memory :  64 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM_32Mx64 Single Rank = 256 MB
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
 PORT fpga_0_Ethernet_MAC_slew1_pin = net_vcc, DIR = O
 PORT fpga_0_Ethernet_MAC_slew2_pin = net_vcc, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO
 PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
 PORT fpga_0_DIPSWs_4Bit_GPIO_IO_pin = fpga_0_DIPSWs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
 PORT fpga_0_PushButtons_5Bit_GPIO_IO_pin = fpga_0_PushButtons_5Bit_GPIO_IO, DIR = IO, VEC = [0:4]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, DIR = O, VEC = [0:2]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, DIR = O, VEC = [0:2]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, DIR = O, VEC = [0:12]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, DIR = O, VEC = [0:1]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = O
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = O
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = O
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, DIR = O, VEC = [0:7]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, DIR = IO, VEC = [0:7]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, DIR = IO, VEC = [0:63]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = O
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = O
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = DCMCLK
 PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = DCMCLK
 PORT sys_rst_pin = sys_rst_s, DIR = I


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_USE_FPU = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 65536
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 65536
 PARAMETER C_ICACHE_BASEADDR = 0x30000000
 PARAMETER C_ICACHE_HIGHADDR = 0x3fffffff
 PARAMETER C_DCACHE_BASEADDR = 0x30000000
 PARAMETER C_DCACHE_HIGHADDR = 0x3fffffff
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_DIV = 1
 PARAMETER C_USE_MSR_INSTR = 1
 PARAMETER C_USE_PCMP_INSTR = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT CLK = sys_clk_s
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
 PORT Interrupt = Interrupt
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 38400
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = RS232_Uart_1_Interrupt
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
END

BEGIN opb_ethernet
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DMA_PRESENT = 3
 PARAMETER C_IPIF_RDFIFO_DEPTH = 32768
 PARAMETER C_IPIF_WRFIFO_DEPTH = 32768
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_BASEADDR = 0x40c00000
 PARAMETER C_HIGHADDR = 0x40c0ffff
 BUS_INTERFACE MSOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
 PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
 PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
END

BEGIN opb_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_MEM_WIDTH = 16
 PARAMETER C_BASEADDR = 0x41800000
 PARAMETER C_HIGHADDR = 0x4180ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END

BEGIN opb_gpio
 PARAMETER INSTANCE = DIPSWs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_DIPSWs_4Bit_GPIO_IO
END

BEGIN opb_gpio
 PARAMETER INSTANCE = PushButtons_5Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_PushButtons_5Bit_GPIO_IO
END

BEGIN opb_ddr
 PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CLK_PAIRS = 4
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 100000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 20000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_TREFC = 70300000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 10
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_DDR_DWIDTH = 64
 PARAMETER C_MEM0_BASEADDR = 0x30000000
 PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
 PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
 PORT Device_Clk90_in = clk_90_s
 PORT Device_Clk90_in_n = clk_90_n_s
 PORT Device_Clk = sys_clk_s
 PORT Device_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = opb_timer_1_Interrupt
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT Irq = Interrupt
 PORT Intr = RS232_Uart_1_Interrupt & SysACE_CompactFlash_SysACE_IRQ & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = sysclk_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = sys_clk_s
 PORT Res = sys_clk_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = clk_90_s
 PORT Res = clk_90_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = ddr_clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = ddr_clk_90_s
 PORT Res = ddr_clk_90_n_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_PHASE_SHIFT = 60
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END

############################################################
# 
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 8.1.01 EDK_I.19.5 
# Description: uClinux Configuration File
# 
############################################################



# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x30000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x10000000

# LMB_MEMORY Settings
define_hex CONFIG_XILINX_LMB_START 0x00000000
define_hex CONFIG_XILINX_LMB_SIZE 0x00010000

# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 100000000

# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex2p
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_FPU 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR 1
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 0
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 0
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x30000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 12
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 65536
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 0
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x30000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 12
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 65536
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 4.00.a

# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x0000FFFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x50000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b

# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x0000FFFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x50000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b

# Definitions for V20_0
define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
define_hex CONFIG_XILINX_V20_0_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_V20_0_HIGHADDR 0x00000000
define_int CONFIG_XILINX_V20_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_V20_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_V20_0_NUM_MASTERS 3
define_int CONFIG_XILINX_V20_0_NUM_SLAVES 10
define_int CONFIG_XILINX_V20_0_USE_LUT_OR 1
define_int CONFIG_XILINX_V20_0_EXT_RESET_HIGH 0
define_int CONFIG_XILINX_V20_0_DYNAM_PRIORITY 0
define_int CONFIG_XILINX_V20_0_PARK 0
define_int CONFIG_XILINX_V20_0_PROINTRFCE 0
define_int CONFIG_XILINX_V20_0_REG_GRANTS 1
define_int CONFIG_XILINX_V20_0_DEV_BLK_ID 0
define_int CONFIG_XILINX_V20_0_DEV_MIR_ENABLE 0
define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
define_string CONFIG_XILINX_V20_0_HW_VER 1.10.c

# Definitions for MDM_0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x41400000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x4140FFFF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY virtex2p
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 1
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a

# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_Uart_1
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x40600000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x4060FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 100000000
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 38400
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_Uart_1
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 3

# Definitions for ETHERNET_0
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
define_int CONFIG_XILINX_ETHERNET_0_DEV_BLK_ID 1
define_int CONFIG_XILINX_ETHERNET_0_DEV_MIR_ENABLE 1
define_hex CONFIG_XILINX_ETHERNET_0_BASEADDR 0x40C00000
define_hex CONFIG_XILINX_ETHERNET_0_HIGHADDR 0x40C0FFFF
define_int CONFIG_XILINX_ETHERNET_0_RESET_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_PRESENT 3
define_int CONFIG_XILINX_ETHERNET_0_DMA_INTR_COALESCE 1
define_int CONFIG_XILINX_ETHERNET_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS 10000
define_string CONFIG_XILINX_ETHERNET_0_FAMILY virtex2p
define_int CONFIG_XILINX_ETHERNET_0_IPIF_RDFIFO_DEPTH 32768
define_int CONFIG_XILINX_ETHERNET_0_IPIF_WRFIFO_DEPTH 32768
define_hex CONFIG_XILINX_ETHERNET_0_MIIM_CLKDVD 0x0000001F
define_int CONFIG_XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_PAD_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_FCS_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_DEPTH 64
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_BRAM_1_SRL_0 0
define_int CONFIG_XILINX_ETHERNET_0_HALF_DUPLEX_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_ERR_COUNT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_CAM_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_CAM_BRAM_0_SRL_1 1
define_int CONFIG_XILINX_ETHERNET_0_JUMBO_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_MII_EXIST 1
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
define_string CONFIG_XILINX_ETHERNET_0_HW_VER 1.02.a
define_int CONFIG_XILINX_ETHERNET_0_IRQ 1

# Definitions for SYSACE_0
define_string CONFIG_XILINX_SYSACE_0_INSTANCE SysACE_CompactFlash
define_hex CONFIG_XILINX_SYSACE_0_BASEADDR 0x41800000
define_hex CONFIG_XILINX_SYSACE_0_HIGHADDR 0x4180FFFF
define_int CONFIG_XILINX_SYSACE_0_MEM_WIDTH 16
define_int CONFIG_XILINX_SYSACE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_SYSACE_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_SYSACE_0_INSTANCE SysACE_CompactFlash
define_string CONFIG_XILINX_SYSACE_0_HW_VER 1.00.c
define_int CONFIG_XILINX_SYSACE_0_IRQ 2

# Definitions for GPIO_0
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x40000000
define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x4000FFFF
define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_0_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 4
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 0
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b

# Definitions for GPIO_1
define_string CONFIG_XILINX_GPIO_1_INSTANCE DIPSWs_4Bit
define_hex CONFIG_XILINX_GPIO_1_BASEADDR 0x40020000
define_hex CONFIG_XILINX_GPIO_1_HIGHADDR 0x4002FFFF
define_int CONFIG_XILINX_GPIO_1_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_1_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_1_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_1_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_1_GPIO_WIDTH 4
define_int CONFIG_XILINX_GPIO_1_ALL_INPUTS 1
define_int CONFIG_XILINX_GPIO_1_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_1_IS_BIDIR 1
define_hex CONFIG_XILINX_GPIO_1_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_1_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_1_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_1_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_1_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_1_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_1_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_1_INSTANCE DIPSWs_4Bit
define_string CONFIG_XILINX_GPIO_1_HW_VER 3.01.b

# Definitions for GPIO_2
define_string CONFIG_XILINX_GPIO_2_INSTANCE PushButtons_5Bit
define_hex CONFIG_XILINX_GPIO_2_BASEADDR 0x40040000
define_hex CONFIG_XILINX_GPIO_2_HIGHADDR 0x4004FFFF
define_int CONFIG_XILINX_GPIO_2_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_2_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_2_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_2_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_2_GPIO_WIDTH 5
define_int CONFIG_XILINX_GPIO_2_ALL_INPUTS 1
define_int CONFIG_XILINX_GPIO_2_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_2_IS_BIDIR 1
define_hex CONFIG_XILINX_GPIO_2_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_2_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_2_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_2_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_2_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_2_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_2_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_2_INSTANCE PushButtons_5Bit
define_string CONFIG_XILINX_GPIO_2_HW_VER 3.01.b

# Definitions for DDR_0
define_string CONFIG_XILINX_DDR_0_INSTANCE DDR_256MB_32MX64_rank1_row13_col10_cl2_5
define_int CONFIG_XILINX_DDR_0_DDR_ASYNSUPPORT 0
define_int CONFIG_XILINX_DDR_0_INCLUDE_BURST_SUPPORT 0
define_int CONFIG_XILINX_DDR_0_REG_DIMM 0
define_int CONFIG_XILINX_DDR_0_EXTRA_TSU 0
define_int CONFIG_XILINX_DDR_0_NUM_BANKS_MEM 1
define_int CONFIG_XILINX_DDR_0_NUM_CLK_PAIRS 4
define_string CONFIG_XILINX_DDR_0_FAMILY virtex2p
define_int CONFIG_XILINX_DDR_0_DDR_TMRD 20000
define_int CONFIG_XILINX_DDR_0_DDR_TWR 20000
define_int CONFIG_XILINX_DDR_0_DDR_TWTR 1
define_int CONFIG_XILINX_DDR_0_DDR_TRAS 60000
define_int CONFIG_XILINX_DDR_0_DDR_TRC 90000
define_int CONFIG_XILINX_DDR_0_DDR_TRFC 100000
define_int CONFIG_XILINX_DDR_0_DDR_TRCD 30000
define_int CONFIG_XILINX_DDR_0_DDR_TRRD 20000
define_int CONFIG_XILINX_DDR_0_DDR_TREFC 70300000
define_int CONFIG_XILINX_DDR_0_DDR_TREFI 7800000
define_int CONFIG_XILINX_DDR_0_DDR_TRP 30000
define_int CONFIG_XILINX_DDR_0_DDR_CAS_LAT 2
define_int CONFIG_XILINX_DDR_0_DDR_DWIDTH 64
define_int CONFIG_XILINX_DDR_0_DDR_AWIDTH 13
define_int CONFIG_XILINX_DDR_0_DDR_COL_AWIDTH 10
define_int CONFIG_XILINX_DDR_0_DDR_BANK_AWIDTH 2
define_hex CONFIG_XILINX_DDR_0_MEM0_BASEADDR 0x30000000
define_hex CONFIG_XILINX_DDR_0_MEM0_HIGHADDR 0x3FFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM2_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM2_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM3_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM3_HIGHADDR 0x00000000
define_int CONFIG_XILINX_DDR_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_CLK_PERIOD_PS 10000
define_int CONFIG_XILINX_DDR_0_SIM_INIT_TIME_PS 200000000
define_string CONFIG_XILINX_DDR_0_INSTANCE DDR_256MB_32MX64_rank1_row13_col10_cl2_5
define_string CONFIG_XILINX_DDR_0_HW_VER 2.00.b

# Definitions for TIMER_0
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_FAMILY virtex2p
define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 0
define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x41C00000
define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x41C0FFFF
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
define_int CONFIG_XILINX_TIMER_0_IRQ 0

# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_FAMILY virtex2p
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x41200000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x4120FFFF
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 4
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000008
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000008
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000007
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c

# Peripheral counts
define_int CONFIG_XILINX_SYSACE_NUM_INSTANCES 1
define_int CONFIG_XILINX_V20_NUM_INSTANCES 1
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
define_int CONFIG_XILINX_DDR_NUM_INSTANCES 1
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 3
define_int CONFIG_XILINX_ETHERNET_NUM_INSTANCES 1

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