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RE: [microblaze-uclinux] microblaze RESET with OS
Hi,
You shouldn't drive the reset port on MicroBlaze directly from the external port.
MicroBlaze needs to get the reset from the opb or lmb bus.
This connection is done automatically with the tools.
So you need to have one reset signal that connects to all bus peripherals (opb_v20 and lmb_v10).
If you using a button for the reset, the signal might need some cleaning so you don't get too many bounces on the signal.
Göran Bilski
-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of Raul Camaras
Sent: Monday, May 29, 2006 17:03
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] microblaze RESET with OS
Hi all!
i need help regarding making a reset on a Microblaze that boots a
uclinux from Flash.
Signal sys_rst_s comes form a external hardware push button.
I changed my system.mhs file so that uclinux boots ok(see below),
but whatever I try(setting other resets in mhs to constants...),
when I push the reset buttong, uclinux hangs up.
How can i just reset MicroBlaze and boot uclinux without turning the
power off and on. I use ISE7.1 and EDK7.1.02i. Thanks!
My mhs file:
> PARAMETER VERSION = 2.1.0
>
>
> PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = INPUT
> PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUTPUT
> #PORT fpga_0_LEDs_4Bit_GPIO_d_out_pin = testleds, VEC = [0:3], DIR = OUTPUT
> # PORT fpga_0_LED_7Segment1_GPIO_d_out_pin = fpga_0_LED_7Segment1_GPIO_d_out, VEC = [0:6], DIR = OUTPUT
> #PORT fpga_0_LED_7Segment2_GPIO_d_out_pin = fpga_0_LED_7Segment2_GPIO_d_out, VEC = [0:6], DIR = OUTPUT
> # PORT fpga_0_Push_Buttons_2Bit_GPIO_in_pin = fpga_0_Push_Buttons_2Bit_GPIO_in, VEC = [0:1], DIR = INPUT
> PORT fpga_0_DIP_Switches_8Bit_GPIO_in_pin = testdips, VEC = [0:7], DIR = INPUT
> PORT fpga_0_FLASH_2Mx16_Mem_A_pin = fpga_0_FLASH_2Mx16_Mem_A, VEC = [10:30], DIR = OUTPUT
> PORT fpga_0_FLASH_2Mx16_Mem_DQ_pin = fpga_0_FLASH_2Mx16_Mem_DQ, VEC = [0:15], DIR = INOUT
> PORT fpga_0_FLASH_2Mx16_Mem_OEN_pin = fpga_0_FLASH_2Mx16_Mem_OEN, VEC = [0:0], DIR = OUTPUT
> PORT fpga_0_Flash_And_Gate_Res_pin = fpga_0_Flash_And_Gate_Res, DIR = OUTPUT
> PORT fpga_0_FLASH_2Mx16_Mem_WEN_pin = fpga_0_FLASH_2Mx16_Mem_WEN, DIR = OUTPUT
> PORT fpga_0_FLASH_2Mx16_Mem_RPN_pin = fpga_0_FLASH_2Mx16_Mem_RPN, DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_Clk_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_Clk, DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_Clkn_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_Clkn, DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_Addr_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_Addr, VEC = [0:12], DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_CASn_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_CASn, DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_CKE_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_CKE, DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_CSn_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_CSn, DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_RASn_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_RASn, DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_WEn_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_WEn, DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_DM_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_DM, VEC = [0:1], DIR = OUTPUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_DQS, VEC = [0:1], DIR = INOUT
> PORT fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_pin = fpga_0_DDR_SDRAM_16Mx16_DDR_DQ, VEC = [0:15], DIR = INOUT
> PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = OUTPUT
> PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = INPUT
> PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = INPUT
> PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = INPUT
> PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = INPUT
> PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, VEC = [3:0], DIR = INPUT
> PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = INPUT
> PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = INPUT
> PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = OUTPUT
> PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, VEC = [3:0], DIR = OUTPUT
> PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = INOUT
> PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = OUTPUT
> PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = INOUT
> PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
> PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
> PORT sys_rst_pin = sys_rst_s, DIR = INPUT
> PORT DDR_Clk_2 = DDR_Clk_2, DIR = O
>
> PORT adc1_data_pin = fpga_adc1_data, VEC = [9:0] , DIR = INPUT
> PORT adc1_m0_pin = fpga_adc1_m0, DIR = OUTPUT
> PORT adc1_m1_pin = fpga_adc1_m1, DIR = OUTPUT
> PORT adc1_rd_pin = fpga_adc1_rd, DIR = OUTPUT
> PORT adc1_wr_pin = fpga_adc1_wr, DIR = OUTPUT
> PORT adc1_conv_start_pin = fpga_adc1_conv_start, DIR = OUTPUT
> PORT adc2_data_pin = fpga_adc2_data, VEC = [9:0] , DIR = INPUT
> PORT adc2_m0_pin = fpga_adc2_m0, DIR = OUTPUT
> PORT adc2_m1_pin = fpga_adc2_m1, DIR = OUTPUT
> PORT adc2_rd_pin = fpga_adc2_rd, DIR = OUTPUT
> PORT adc2_wr_pin = fpga_adc2_wr, DIR = OUTPUT
> PORT adc2_conv_start_pin = fpga_adc2_conv_start, DIR = OUTPUT
> # PORT ERROR_ACK_pin = fpga_ERROR_ACK, DIR = INPUT
> PORT ERR_ACK_SWITCH = fpga_ERR_ACK_PIN, DIR = INPUT
> # PORT EXT_IGBT_START_pin = fpga_EXT_IGBT_START, DIR = INPUT
> PORT COMP_MODE_SWITCH = fpga_COMP_MODE_PIN, DIR = INPUT
> # PORT EXT_START_pin = fpga_EXT_START, DIR = INPUT
> PORT START_STOP_SWITCH = fpga_START_STOP_PIN, DIR = INPUT
> # COMP_ENABLE
> # PORT comp_mode_pin = fpga_comp_mode_pin, DIR = INPUT
> PORT LOCAL_REMOTE_SWITCH = fpga_LOCAL_REMOTE_PIN, DIR = INPUT
> PORT ERROR_INVERTER_pin = fpga_ERROR_INVERTER, DIR = OUTPUT
> PORT ERROR_SCADA_pin = fpga_ERROR_SCADA, DIR = OUTPUT
> PORT MAIN_REL_pin = fpga_MAIN_REL, DIR = OUTPUT
> PORT PRECHARGE_REL_pin = fpga_PRECHARGE_REL, DIR = OUTPUT
> PORT READY_SCADA_pin = fpga_READY_SCADA, DIR = OUTPUT
> PORT RUN_INVERTER_pin = fpga_RUN_INVERTER, DIR = OUTPUT
> PORT RUN_SCADA_pin = fpga_RUN_SCADA, DIR = OUTPUT
> PORT WAIT_FOR_ACK_pin = fpga_WAIT_FOR_ACK, DIR = OUTPUT
> PORT ERR_IGBT1_pin = fpga_ERR_IGBT1, DIR = INPUT
> PORT ERR_IGBT2_pin = fpga_ERR_IGBT2, DIR = INPUT
> PORT ERR_IGBT3_pin = fpga_ERR_IGBT3, DIR = INPUT
> PORT ERR_IGBT4_pin = fpga_ERR_IGBT4, DIR = INPUT
> PORT ERR_IGBT5_pin = fpga_ERR_IGBT5, DIR = INPUT
> PORT ERR_IGBT6_pin = fpga_ERR_IGBT6, DIR = INPUT
> PORT ERR_IGBT7_pin = fpga_ERR_IGBT7, DIR = INPUT
> PORT ERR_IGBT8_pin = fpga_ERR_IGBT8, DIR = INPUT
> PORT ERR_IGBT9_pin = fpga_ERR_IGBT9, DIR = INPUT
> PORT ERR_IGBT10_pin = fpga_ERR_IGBT10, DIR = INPUT
> PORT ERR_IGBT11_pin = fpga_ERR_IGBT11, DIR = INPUT
> PORT ERR_IGBT12_pin = fpga_ERR_IGBT12, DIR = INPUT
> # PORT INVERTER_ENABLE_EXT_pin = fpga_inverter_enable_ext, DIR = INPUT
> # PORT INVERTER_ENABLE_pin = fpga_INVERTER_ENABLE, DIR = OUTPUT
> # PORT AUX_FIBRE_OUT_EN_pin = fpga_AUX_FIBRE_OUT_EN, DIR = OUTPUT
> PORT SCADA_ENABLE_pin = fpga_SCADA_ENABLE, DIR = OUTPUT
> PORT INV_FIBRE_ENABLE_pin = fpga_INV_FIBRE_ENABLE, DIR = OUTPUT
> PORT A0_OUT_pin = fpga_A0_OUT, DIR = OUTPUT
> PORT A1_OUT_pin = fpga_A1_OUT, DIR = OUTPUT
> PORT A2_OUT_pin = fpga_A2_OUT, DIR = OUTPUT
> PORT CS_OUT_pin = fpga_CS_OUT, DIR = OUTPUT
> PORT LVL_OUT_pin = fpga_LVL_OUT, DIR = OUTPUT
> PORT RESET_OUT_pin = fpga_RESET_OUT, DIR = OUTPUT
> PORT EXT_POWER_GOOD_pin = fpga_EXT_POWER_GOOD, DIR = INPUT
> PORT DIG_POWER_GOOD_pin = fpga_DIG_POWER_GOOD, DIR = INPUT
> PORT ANA_POWER_GOOD_pin = fpga_ANA_POWER_GOOD, DIR = INPUT
> PORT TRANS_GROUPA_pin = fpga_TRANS_GROUPA, DIR = INPUT
> PORT TRANS_GROUPB_pin = fpga_TRANS_GROUPB, DIR = INPUT
> PORT TRANS_GROUPC_pin = fpga_TRANS_GROUPC, DIR = INPUT
> PORT adc1_fast_currents_data_pin = fpga_adc1_fast_currents_data, VEC = [9:0] , DIR = INPUT
> PORT adc2_fast_currents_data_pin = fpga_adc2_fast_currents_data, VEC = [9:0] , DIR = INPUT
> PORT adc1_fast_currents_clk_pin = fpga_adc1_fast_currents_clk, DIR = OUTPUT
> PORT adc1_fast_currents_select_pin = fpga_adc1_fast_currents_select, DIR = OUTPUT
> PORT adc2_fast_currents_clk_pin = fpga_adc2_fast_currents_clk, DIR = OUTPUT
> PORT adc2_fast_currents_select_pin = fpga_adc2_fast_currents_select, DIR = OUTPUT
> PORT igbt1_pin = fpga_igbt1, DIR = OUTPUT
> PORT igbt2_pin = fpga_igbt2, DIR = OUTPUT
> PORT igbt3_pin = fpga_igbt3, DIR = OUTPUT
> PORT igbt4_pin = fpga_igbt4, DIR = OUTPUT
> PORT igbt5_pin = fpga_igbt5, DIR = OUTPUT
> PORT igbt6_pin = fpga_igbt6, DIR = OUTPUT
> PORT igbt7_pin = fpga_igbt7, DIR = OUTPUT
> PORT igbt8_pin = fpga_igbt8, DIR = OUTPUT
> PORT igbt9_pin = fpga_igbt9, DIR = OUTPUT
> PORT igbt10_pin = fpga_igbt10, DIR = OUTPUT
> PORT igbt11_pin = fpga_igbt11, DIR = OUTPUT
> PORT igbt12_pin = fpga_igbt12, DIR = OUTPUT
> # PORT id_soll_out_pin = fpga_id_soll_out, DIR = OUTPUT
> # PORT ud_diff_out_pin = fpga_ud_diff_out, DIR = OUTPUT
> # PORT x_u_pin = fpga_x_u, DIR = OUTPUT
>
>
> BEGIN inverter
> PARAMETER INSTANCE = reset_inverter
> PARAMETER HW_VER = 1.00.a
> PORT rst_in = sys_rst_s
> PORT rst_out = sys_nrst_s
> PORT vcc = vcc_s
> END
>
> BEGIN microblaze
> PARAMETER INSTANCE = microblaze_0
> PARAMETER HW_VER = 4.00.a
> PARAMETER C_DEBUG_ENABLED = 1
> PARAMETER C_NUMBER_OF_PC_BRK = 2
> PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
> PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
> PARAMETER C_USE_ICACHE = 1
> PARAMETER C_CACHE_BYTE_SIZE = 8192
> PARAMETER C_USE_DCACHE = 1
> PARAMETER C_DCACHE_BYTE_SIZE = 8192
> PARAMETER C_ICACHE_BASEADDR = 0x22000000
> PARAMETER C_ICACHE_HIGHADDR = 0x23ffffff
> PARAMETER C_ADDR_TAG_BITS = 12
> PARAMETER C_DCACHE_BASEADDR = 0x22000000
> PARAMETER C_DCACHE_HIGHADDR = 0x23ffffff
> PARAMETER C_DCACHE_ADDR_TAG = 12
> PARAMETER C_FSL_LINKS = 1
> BUS_INTERFACE DLMB = dlmb
> BUS_INTERFACE ILMB = ilmb
> BUS_INTERFACE DOPB = mb_opb
> BUS_INTERFACE IOPB = mb_opb
> BUS_INTERFACE SFSL0 = fsl_v20_0
> PORT CLK = sys_clk_s
> PORT RESET = sys_nrst_s
> PORT DBG_CAPTURE = DBG_CAPTURE_s
> PORT DBG_CLK = DBG_CLK_s
> PORT DBG_REG_EN = DBG_REG_EN_s
> PORT DBG_TDI = DBG_TDI_s
> PORT DBG_TDO = DBG_TDO_s
> PORT DBG_UPDATE = DBG_UPDATE_s
> PORT Interrupt = Interrupt
> END
>
> BEGIN opb_v20
> PARAMETER INSTANCE = mb_opb
> PARAMETER HW_VER = 1.10.c
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT SYS_Rst = vcc_s # sys_rst_s
> PORT OPB_Clk = sys_clk_s
> END
>
> BEGIN opb_mdm
> PARAMETER INSTANCE = debug_module
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_MB_DBG_PORTS = 1
> PARAMETER C_USE_UART = 1
> PARAMETER C_UART_WIDTH = 8
> PARAMETER C_BASEADDR = 0x41400000
> PARAMETER C_HIGHADDR = 0x4140ffff
> PARAMETER C_WRITE_FSL_PORTS = 1
> BUS_INTERFACE SOPB = mb_opb
> BUS_INTERFACE MFSL0 = fsl_v20_0
> PORT OPB_Clk = sys_clk_s
> PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
> PORT DBG_CLK_0 = DBG_CLK_s
> PORT DBG_REG_EN_0 = DBG_REG_EN_s
> PORT DBG_TDI_0 = DBG_TDI_s
> PORT DBG_TDO_0 = DBG_TDO_s
> PORT DBG_UPDATE_0 = DBG_UPDATE_s
> END
>
> BEGIN lmb_v10
> PARAMETER INSTANCE = ilmb
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT SYS_Rst = vcc_s # sys_rst_s
> PORT LMB_Clk = sys_clk_s
> END
>
> BEGIN lmb_v10
> PARAMETER INSTANCE = dlmb
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT SYS_Rst = vcc_s # sys_rst_s
> PORT LMB_Clk = sys_clk_s
> END
>
> BEGIN lmb_bram_if_cntlr
> PARAMETER INSTANCE = dlmb_cntlr
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_BASEADDR = 0x00000000
> PARAMETER C_HIGHADDR = 0x00001fff
> BUS_INTERFACE SLMB = dlmb
> BUS_INTERFACE BRAM_PORT = dlmb_port
> END
>
> BEGIN lmb_bram_if_cntlr
> PARAMETER INSTANCE = ilmb_cntlr
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_BASEADDR = 0x00000000
> PARAMETER C_HIGHADDR = 0x00001fff
> BUS_INTERFACE SLMB = ilmb
> BUS_INTERFACE BRAM_PORT = ilmb_port
> END
>
> BEGIN bram_block
> PARAMETER INSTANCE = lmb_bram
> PARAMETER HW_VER = 1.00.a
> BUS_INTERFACE PORTA = ilmb_port
> BUS_INTERFACE PORTB = dlmb_port
> END
>
> BEGIN opb_uartlite
> PARAMETER INSTANCE = RS232
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_BAUDRATE = 115200
> PARAMETER C_DATA_BITS = 8
> PARAMETER C_ODD_PARITY = 0
> PARAMETER C_USE_PARITY = 0
> PARAMETER C_CLK_FREQ = 75000000
> PARAMETER C_BASEADDR = 0x40600000
> PARAMETER C_HIGHADDR = 0x4060ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT Interrupt = RS232_Interrupt
> PORT RX = fpga_0_RS232_RX
> PORT TX = fpga_0_RS232_TX
> END
>
> BEGIN main
> PARAMETER INSTANCE = main_testcore
> PARAMETER HW_VER = 1.00.a
> PORT clk = sys_clk_s
> PORT adc1_data = fpga_adc1_data
> PORT adc1_m0 = fpga_adc1_m0
> PORT adc1_m1 = fpga_adc1_m1
> PORT adc1_rd = fpga_adc1_rd
> PORT adc1_wr = fpga_adc1_wr
> PORT adc1_conv_start = fpga_adc1_conv_start
> PORT adc2_data = fpga_adc2_data
> PORT adc2_m0 = fpga_adc2_m0
> PORT adc2_m1 = fpga_adc2_m1
> PORT adc2_rd = fpga_adc2_rd
> PORT adc2_wr = fpga_adc2_wr
> PORT adc2_conv_start = fpga_adc2_conv_start
> PORT ERR_ACK_PIN = fpga_ERR_ACK_PIN
> PORT COMP_MODE_PIN = fpga_COMP_MODE_PIN
> PORT LOCAL_REMOTE_PIN = fpga_LOCAL_REMOTE_PIN
> PORT START_STOP_PIN = fpga_START_STOP_PIN
> PORT ERROR_INVERTER = fpga_ERROR_INVERTER
> PORT ERROR_SCADA = fpga_ERROR_SCADA
> PORT MAIN_REL = fpga_MAIN_REL
> PORT PRECHARGE_REL = fpga_PRECHARGE_REL
> PORT READY_SCADA = fpga_READY_SCADA
> PORT RUN_INVERTER = fpga_RUN_INVERTER
> PORT RUN_SCADA = fpga_RUN_SCADA
> PORT WAIT_FOR_ACK = fpga_WAIT_FOR_ACK
> PORT ERR_IGBT1 = fpga_ERR_IGBT1
> PORT ERR_IGBT2 = fpga_ERR_IGBT2
> PORT ERR_IGBT3 = fpga_ERR_IGBT3
> PORT ERR_IGBT4 = fpga_ERR_IGBT4
> PORT ERR_IGBT5 = fpga_ERR_IGBT5
> PORT ERR_IGBT6 = fpga_ERR_IGBT6
> PORT ERR_IGBT7 = fpga_ERR_IGBT7
> PORT ERR_IGBT8 = fpga_ERR_IGBT8
> PORT ERR_IGBT9 = fpga_ERR_IGBT9
> PORT ERR_IGBT10 = fpga_ERR_IGBT10
> PORT ERR_IGBT11 = fpga_ERR_IGBT11
> PORT ERR_IGBT12 = fpga_ERR_IGBT12
> # PORT INVERTER_ENABLE_EXT = fpga_inverter_enable_ext
> # PORT INVERTER_ENABLE = fpga_INVERTER_ENABLE
> # PORT AUX_FIBRE_OUT_EN = fpga_AUX_FIBRE_OUT_EN
> PORT SCADA_ENABLE = fpga_SCADA_ENABLE
> PORT INV_FIBRE_ENABLE = fpga_INV_FIBRE_ENABLE
> PORT A0_OUT = fpga_A0_OUT
> PORT A1_OUT = fpga_A1_OUT
> PORT A2_OUT = fpga_A2_OUT
> PORT CS_OUT = fpga_CS_OUT
> PORT LVL_OUT = fpga_LVL_OUT
> PORT RESET_OUT = fpga_RESET_OUT
> PORT EXT_POWER_GOOD = fpga_EXT_POWER_GOOD
> PORT DIG_POWER_GOOD = fpga_DIG_POWER_GOOD
> PORT ANA_POWER_GOOD = fpga_ANA_POWER_GOOD
> PORT TRANS_GROUPA = fpga_TRANS_GROUPA
> PORT TRANS_GROUPB = fpga_TRANS_GROUPB
> PORT TRANS_GROUPC = fpga_TRANS_GROUPC
> PORT adc1_fast_currents_data = fpga_adc1_fast_currents_data
> PORT adc2_fast_currents_data = fpga_adc2_fast_currents_data
> PORT adc1_fast_currents_clk = fpga_adc1_fast_currents_clk
> PORT adc1_fast_currents_select = fpga_adc1_fast_currents_select
> PORT adc2_fast_currents_clk = fpga_adc2_fast_currents_clk
> PORT adc2_fast_currents_select = fpga_adc2_fast_currents_select
> PORT igbt1 = fpga_igbt1
> PORT igbt2 = fpga_igbt2
> PORT igbt3 = fpga_igbt3
> PORT igbt4 = fpga_igbt4
> PORT igbt5 = fpga_igbt5
> PORT igbt6 = fpga_igbt6
> PORT igbt7 = fpga_igbt7
> PORT igbt8 = fpga_igbt8
> PORT igbt9 = fpga_igbt9
> PORT igbt10 = fpga_igbt10
> PORT igbt11 = fpga_igbt11
> PORT igbt12 = fpga_igbt12
> # PORT id_soll_out = fpga_id_soll_out
> # PORT ud_diff_out = fpga_ud_diff_out
> # PORT x_u = fpga_x_u
> PORT address = address
> PORT data_read = data_read
> PORT data_write = data_write
> END
>
> BEGIN opb_gpio
> PARAMETER INSTANCE = LEDs_4Bit
> PARAMETER HW_VER = 3.01.b
> PARAMETER C_GPIO_WIDTH = 4
> PARAMETER C_IS_DUAL = 0
> PARAMETER C_ALL_INPUTS = 0
> PARAMETER C_IS_BIDIR = 0
> PARAMETER C_BASEADDR = 0x40020000
> PARAMETER C_HIGHADDR = 0x4002ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT GPIO_d_out = leds_from_mb
> END
>
> BEGIN opb_gpio
> PARAMETER INSTANCE = LED_7Segment1
> PARAMETER HW_VER = 3.01.b
> PARAMETER C_GPIO_WIDTH = 16
> PARAMETER C_IS_DUAL = 0
> PARAMETER C_ALL_INPUTS = 1
> PARAMETER C_IS_BIDIR = 0
> PARAMETER C_BASEADDR = 0x40060000
> PARAMETER C_HIGHADDR = 0x4006ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT GPIO_in = data_read # fpga_0_LED_7Segment1_GPIO_d_out
> END
>
> BEGIN opb_gpio
> PARAMETER INSTANCE = LED_7Segment2
> PARAMETER HW_VER = 3.01.b
> PARAMETER C_GPIO_WIDTH = 16
> PARAMETER C_IS_DUAL = 0
> PARAMETER C_ALL_INPUTS = 0
> PARAMETER C_IS_BIDIR = 0
> PARAMETER C_BASEADDR = 0x40040000
> PARAMETER C_HIGHADDR = 0x4004ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT GPIO_d_out = data_write # fpga_0_LED_7Segment2_GPIO_d_out
> END
>
> BEGIN opb_gpio
> PARAMETER INSTANCE = Push_Buttons_2Bit
> PARAMETER HW_VER = 3.01.b
> PARAMETER C_GPIO_WIDTH = 16
> PARAMETER C_IS_DUAL = 0
> PARAMETER C_ALL_INPUTS = 0
> PARAMETER C_IS_BIDIR = 0
> PARAMETER C_BASEADDR = 0x40000000
> PARAMETER C_HIGHADDR = 0x4000ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT GPIO_d_out = address # fpga_0_Push_Buttons_2Bit_GPIO_in
> END
>
> BEGIN opb_gpio
> PARAMETER INSTANCE = DIP_Switches_8Bit
> PARAMETER HW_VER = 3.01.b
> PARAMETER C_GPIO_WIDTH = 8
> PARAMETER C_IS_DUAL = 0
> PARAMETER C_ALL_INPUTS = 1
> PARAMETER C_IS_BIDIR = 0
> PARAMETER C_BASEADDR = 0x40080000
> PARAMETER C_HIGHADDR = 0x4008ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT GPIO_in = testdips
> END
>
> BEGIN opb_emc
> PARAMETER INSTANCE = FLASH_2Mx16
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_OPB_CLK_PERIOD_PS = 13333
> PARAMETER C_NUM_BANKS_MEM = 1
> PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
> PARAMETER C_SYNCH_MEM_0 = 0
> PARAMETER C_MEM0_WIDTH = 16
> PARAMETER C_MAX_MEM_WIDTH = 16
> PARAMETER C_TCEDV_PS_MEM_0 = 70000
> PARAMETER C_TWC_PS_MEM_0 = 35000
> PARAMETER C_TAVDV_PS_MEM_0 = 70000
> PARAMETER C_TWP_PS_MEM_0 = 35000
> PARAMETER C_THZCE_PS_MEM_0 = 0
> PARAMETER C_TLZWE_PS_MEM_0 = 0
> PARAMETER C_MEM0_BASEADDR = 0x21000000
> PARAMETER C_MEM0_HIGHADDR = 0x213fffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT Mem_A = fpga_0_FLASH_2Mx16_Mem_A_split
> PORT Mem_DQ = fpga_0_FLASH_2Mx16_Mem_DQ
> PORT Mem_WEN = fpga_0_FLASH_2Mx16_Mem_WEN
> PORT Mem_OEN = fpga_0_FLASH_2Mx16_Mem_OEN
> PORT Mem_BEN = FLASH_2Mx16_Mem_BEN_Flash_And_Gate_Op1
> PORT Mem_RPN = fpga_0_FLASH_2Mx16_Mem_RPN
> END
>
> BEGIN opb_ddr
> PARAMETER INSTANCE = DDR_SDRAM_16Mx16
> PARAMETER HW_VER = 2.00.b
> PARAMETER C_OPB_CLK_PERIOD_PS = 13333
> PARAMETER C_REG_DIMM = 0
> PARAMETER C_DDR_TMRD = 15000
> PARAMETER C_DDR_TWR = 15000
> PARAMETER C_DDR_TWTR = 1
> PARAMETER C_DDR_TRAS = 40000
> PARAMETER C_DDR_TRC = 65000
> PARAMETER C_DDR_TRFC = 75000
> PARAMETER C_DDR_TRCD = 20000
> PARAMETER C_DDR_TRRD = 15000
> PARAMETER C_DDR_TRP = 20000
> PARAMETER C_DDR_TREFC = 70300
> PARAMETER C_DDR_TREFI = 7800000
> PARAMETER C_DDR_DWIDTH = 16
> PARAMETER C_DDR_AWIDTH = 13
> PARAMETER C_DDR_COL_AWIDTH = 9
> PARAMETER C_DDR_BANK_AWIDTH = 2
> PARAMETER C_MEM0_BASEADDR = 0x22000000
> PARAMETER C_MEM0_HIGHADDR = 0x23ffffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT DDR_Clk = fpga_0_DDR_SDRAM_16Mx16_DDR_Clk
> PORT DDR_Clkn = fpga_0_DDR_SDRAM_16Mx16_DDR_Clkn
> PORT DDR_Addr = fpga_0_DDR_SDRAM_16Mx16_DDR_Addr
> PORT DDR_BankAddr = fpga_0_DDR_SDRAM_16Mx16_DDR_BankAddr
> PORT DDR_CASn = fpga_0_DDR_SDRAM_16Mx16_DDR_CASn
> PORT DDR_CKE = fpga_0_DDR_SDRAM_16Mx16_DDR_CKE
> PORT DDR_CSn = fpga_0_DDR_SDRAM_16Mx16_DDR_CSn
> PORT DDR_RASn = fpga_0_DDR_SDRAM_16Mx16_DDR_RASn
> PORT DDR_WEn = fpga_0_DDR_SDRAM_16Mx16_DDR_WEn
> PORT DDR_DM = fpga_0_DDR_SDRAM_16Mx16_DDR_DM
> PORT DDR_DQS = fpga_0_DDR_SDRAM_16Mx16_DDR_DQS
> PORT DDR_DQ = fpga_0_DDR_SDRAM_16Mx16_DDR_DQ
> PORT Device_Clk90_in = clk_90_s
> PORT Device_Clk90_in_n = clk_90_n_s
> PORT Device_Clk = sys_clk_s
> PORT Device_Clk_n = sys_clk_n_s
> PORT DDR_Clk90_in = ddr_clk_90_s
> PORT DDR_Clk90_in_n = ddr_clk_90_n_s
> END
>
> BEGIN opb_ethernet
> PARAMETER INSTANCE = Ethernet_MAC
> PARAMETER HW_VER = 1.02.a
> PARAMETER C_DMA_PRESENT = 1
> PARAMETER C_IPIF_RDFIFO_DEPTH = 32768
> PARAMETER C_IPIF_WRFIFO_DEPTH = 32768
> PARAMETER C_OPB_CLK_PERIOD_PS = 13333
> PARAMETER C_DMA_INTR_COALESCE = 1
> PARAMETER C_BASEADDR = 0x40c00000
> PARAMETER C_HIGHADDR = 0x40c0ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
> PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
> PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
> PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
> PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
> PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
> PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
> PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
> PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
> PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
> PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
> PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
> PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
> PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
> END
>
> BEGIN opb_timer
> PARAMETER INSTANCE = opb_timer_1
> PARAMETER HW_VER = 1.00.b
> PARAMETER C_COUNT_WIDTH = 32
> PARAMETER C_ONE_TIMER_ONLY = 1
> PARAMETER C_BASEADDR = 0x41c00000
> PARAMETER C_HIGHADDR = 0x41c0ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT Interrupt = opb_timer_1_Interrupt
> END
>
> BEGIN opb_intc
> PARAMETER INSTANCE = opb_intc_0
> PARAMETER HW_VER = 1.00.c
> PARAMETER C_BASEADDR = 0x41200000
> PARAMETER C_HIGHADDR = 0x4120ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT Irq = Interrupt
> PORT Intr = RS232_Interrupt & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt
> END
>
> BEGIN util_reduced_logic
> PARAMETER INSTANCE = Flash_And_Gate
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_OPERATION = and
> PARAMETER C_SIZE = 2
> PORT Op1 = FLASH_2Mx16_Mem_BEN_Flash_And_Gate_Op1
> PORT Res = fpga_0_Flash_And_Gate_Res
> END
>
> BEGIN util_bus_split
> PARAMETER INSTANCE = FLASH_2Mx16_util_bus_split_0
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_SIZE_IN = 32
> PARAMETER C_LEFT_POS = 10
> PARAMETER C_SPLIT = 31
> PORT Sig = fpga_0_FLASH_2Mx16_Mem_A_split
> PORT Out1 = fpga_0_FLASH_2Mx16_Mem_A
> END
>
> BEGIN util_vector_logic
> PARAMETER INSTANCE = sysclk_inv
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_SIZE = 1
> PARAMETER C_OPERATION = not
> PORT Op1 = sys_clk_s
> PORT Res = sys_clk_n_s
> END
>
> BEGIN util_vector_logic
> PARAMETER INSTANCE = clk90_inv
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_SIZE = 1
> PARAMETER C_OPERATION = not
> PORT Op1 = clk_90_s
> PORT Res = clk_90_n_s
> END
>
> BEGIN util_vector_logic
> PARAMETER INSTANCE = ddr_clk90_inv
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_SIZE = 1
> PARAMETER C_OPERATION = not
> PORT Op1 = ddr_clk_90_s
> PORT Res = ddr_clk_90_n_s
> END
>
> BEGIN dcm_module
> PARAMETER INSTANCE = dcm_0
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_CLK0_BUF = TRUE
> PARAMETER C_CLK90_BUF = TRUE
> PARAMETER C_CLKIN_PERIOD = 13.333333
> PARAMETER C_CLK_FEEDBACK = 1X
> PARAMETER C_EXT_RESET_HIGH = 1
> PORT CLKIN = dcm_clk_s
> PORT CLK0 = sys_clk_s
> PORT CLK90 = clk_90_s
> PORT CLKFB = sys_clk_s
> PORT RST = net_gnd
> PORT LOCKED = dcm_0_lock
> END
>
> BEGIN dcm_module
> PARAMETER INSTANCE = dcm_1
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_CLK0_BUF = TRUE
> PARAMETER C_CLK90_BUF = TRUE
> PARAMETER C_CLKIN_PERIOD = 13.333333
> PARAMETER C_CLK_FEEDBACK = 1X
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT CLKIN = ddr_feedback_s
> PORT CLK90 = ddr_clk_90_s
> PORT CLK0 = dcm_1_FB
> PORT CLKFB = dcm_1_FB
> PORT RST = dcm_0_lock
> PORT LOCKED = dcm_1_lock
> END
>
> BEGIN replicate_ddrclk_output
> PARAMETER INSTANCE = ddrclk_fb_gen
> PARAMETER HW_VER = 1.00.a
> PORT clk90_in = clk_90_s
> PORT clk270_in = clk_90_n_s
> PORT DDR_Clk_2 = DDR_Clk_2
> END
>
> BEGIN fsl_v20
> PARAMETER INSTANCE = fsl_v20_0
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT FSL_CLK = sys_clk_s
> PORT SYS_RST = vcc_s # sys_rst_s
> END
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___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/