Hi, Babu.
I guess I'm confused. I'm new to the Xilinx parts and cores. But, isn't the
DMA included in the opb_ethernet core when C_DMA_PRESENT is set to 2 or 3?
Table 5 of the opb_ethernet product specification
(http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_ethernet.pdf) lists
the DMA registers that are included when the C_DMA_PRESENT parameter is set
to include DMA functionality.
If the DMA actually requires another core, wouldn't the product
specification say so? Of course, I haven't been impressed by the Xilinx
documentation so far. :-(
I went looking for the mch_ddr reference design, and haven't found it yet.
Is mch_ddr the actual name of the design, or is it some kind of shorthand
for what the real name is (searching for mch_ddr gets me nowhere on the
Xilinx site)?
Thanks.
Kevin Thies
> -----Original Message-----
> From: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-
> uclinux@xxxxxxxxxxxxxx] On Behalf Of Sarath Babu
> Sent: Saturday, July 15, 2006 10:21 PM
> To: microblaze-uclinux@xxxxxxxxxxxxxx
> Subject: Re: [microblaze-uclinux] [patch] Ethernet driver update
>
> Kevin:
> I haven't tried the patch yet. But, there is problem with your HW
> spec, its missing a DMA controller (How would DMA work without a DMA
> controller?). Please look in to some of the DMA based ref designs (the
> mch_ddr one for instance) available from Xilinx's web site.
>
>
> -Babu.
>
> On 7/14/06, Kevin Thies <kthies@xxxxxxxxxxxxxxxxx> wrote:
> > Hi.
> >
> > I'm using an Avnet Spartan-3 Development Board (model ADS-XLX-SP3-
> DEV2000,
> > if anyone cares :-). I have been running uClinux on it for about 2 weeks
> > now. Development environment is EDK8.1.02i on Windows XP Pro, with
> CoLinux
> > installed on the XP box running Debian for the uClinux builds. I'm using
> the
> > current CVS uClinux source.
> >
> > I started out using the opb_ethernet 1.02.a core, with no DMA. This
> > configuration works fine (about 8mbit/sec). When I tried this core with
> > SGDMA, it didn't work for long (I was able to ping, but as soon as I do
> > anything else XMD reports "ERROR:MDT - MicroBlaze Pipeline Stalled
> executing
> > Instruction at >> PC: 0x800xxxxx Try Resetting the Processor to
> > Continue.."). I did not have the patch applied for this configuration.
> >
> > I upgraded to the opb_ethernet 1.04.a core, and applied the patch. Same
> > story, works fine with no DMA. If I try to use Simple DMA or SGDMA, then
> the
> > system is unstable. I get the "Pipeline Stalled" message, or I may get
> "Jan
> > 1 00:01:04 dhcpcd[33]: timed out waiting for a valid DHCP server
> response",
> > after which I can set up the interface manually (ifconfig eth0
> 192.168.0.139
> > netmask 255.255.255.0), and then I get the "Pipeline Stalled" message if
> I
> > try to ping or perform other network traffic.
> >
> > Anyone have any ideas? I'm attaching the hardware specification,
> software
> > specification, and constraint files for my EDK project.
> >
> > Thanks.
> >
> > Kevin Thies
> >
> > > -----Original Message-----
> > > From: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-
> microblaze-
> > > uclinux@xxxxxxxxxxxxxx] On Behalf Of John Williams
> > > Sent: Thursday, June 22, 2006 6:10 PM
> > > To: microblaze-uclinux@xxxxxxxxxxxxxx
> > > Subject: [microblaze-uclinux] [patch] Ethernet driver update
> > >
> > > Hi,
> > >
> > > Attached is a patch on the Xilinx ethernet driver and supporting
> > > xilinx_ocp
> > > files, that applies cleanly on current CVS head.
> > >
> > > If those who are experiencing issues with the ethernet driver could
> please
> > > test
> > > it out and report their findings back to the list, that would be
> greatly
> > > appreciated. Once it gets the all clear I'll commit to CVS.
> > >
> > > Features:
> > >
> > > - Support most recent Xilinx EMAC core, and back-compatible to
> earlier
> > > versions
> > > - Support hardware TCP checksum offload and data realignment engine
> (DRE)
> > > if
> > > enabled on the EMAC core (auto-config'd of course)
> > > - Minor cleanup and revup of Xilinx level 0/1 drivers
> > >
> > > Thanks to Vasanth from Xilinx who did most of the work on this,
> including
> > > merging the TCP offload and DRE support from the PPC drivers.
> > >
> > > With a full SGDMA, checksum offlaod and DRE configuration, raw TCP
> > > throughput
> > > around 50Mbps is achievable on 100MHz MicroBlaze uClinux designs.
> > >
> > > Thanks,
> > >
> > > John
> > > --
> > > Dr John Williams, Research Fellow,
> > > Embedded Systems Group / Reconfigurable Computing
> > > School of ITEE, The University of Queensland, Brisbane, Australia
> > > (p) +61 7 33652185 (f) +61 7 33654999 (m) +61 403969243
> >
> >
> >
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