[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[microblaze-uclinux] OPB DDR SDRAM controller locks the OPB with multiple masters.
I have been working with the OPB DDR SDRAM controller with a bus-master DMA
unit in addition to the processor. I am writing to this list to provide the
community with the information I have discovered. The opb_ddr component in
the EDK 8.1 hardware library has a bug in the ipic_pipe.vhd file. The
ipic_pipe ignores the OPB_retry signal when it is in the case
WAIT_SINGLE_ADDRACK, which happens with any single read or write transaction
to the DDR SDRAM. The effect of the bug is that the OPB locks. If the
processor accesses the DDR SDRAM it will be locked waiting for the
transaction to complete. The transaction will never complete. If you are
using the OPB DDR SDRAM with only one master on the bus you will not see the
I have had a good deal of trouble working with Xilinx's tech support on this
one. Eventually I was able to track down the problem myself, and came up
with a patch for the OPB DDR SDRAM that works for the subset of its features
that I am using.
If anyone wants details about the error, I would be happy to provide them. I
do not have a general solution to the problem. I just wanted this community
to be aware of the problem so anyone who is attempting to use multiple
masters on an OPB knows what is going on. Xilinx's developers should have a
corrected ipic_pipe component at some time in the future, but I do not know
Roger W. Cover
Spectral Instruments, Inc.
420 N. Bonita Ave.
Tucson, AZ 85745
Voice: 520-884-8821 ext. 144
microblaze-uclinux mailing list
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/