RE: [microblaze-uclinux] OPB DDR SDRAM controller locks the OPB with multiple masters.

["Roger W. Cover" <rcover@xxxxxxxxxxxx>]

Greetings,

First let me address the MCH_OPB_DDR core. I have not used it. I did look at
the source. It is organized very differently from the opb_ddr core. It is
not obvious from my inspection that the same error exists in the MCH_OPB_DDR
core. Sorry I am not able to be more helpful on that issue.

The specific effect I encountered was that my DMA would initiate a write
transaction, which would, at some point, be interrupted by an OPB_retry
(SDRAM refresh). When the retry period was over, the CPU would get the bus
because it was higher priority. When the CPU performed an SDRAM read at this
point the problem would occur.

Because of the bug in ipic_pipe.vhd, the Bus2Ip_WrReq signal into the
ddr_controller was left true after OPB_retry was asserted. This caused a
great deal of confusion for the ddr_controller when the CPU performed a
read. The ddr_controller would lock-up in an intermediate state (WAIT_TWR).
Any access to the OPB after that locked the bus because the opb_ddr core
asserted OPB_toutSup but never asserted OPB_xferAck or OPB_retry.

My patch is as follows, beginning with line 747 of ipic_pipe.vhd:
------------------------ WAIT_SINGLE_ADDRACK --------------------
when WAIT_SINGLE_ADDRACK =>

    -- Wait for Ack from IP
    if (IP2Pipe_AddrAck = '1') then

        -- generate AddrACK
        addrack <= '1';
        rdwr_req_done <= '1';

        -- done!
        addrpipe_ns <= ADDRPIPE_IDLE;

    elsif (IP2Pipe_Retry='1') then --<====== NEW
        rdwr_req_done <= '1'; --<====== NEW
        addrpipe_ns <= ADDRPIPE_IDLE; --<====== NEW

    -- If Abort occurs or wrreq goes low,
    -- go to ADDRPIPE_IDLE state.
    elsif  (wrreq_fe = '1') then

        addrpipe_ns <= ADDRPIPE_IDLE;

    end if;

------------------------ WAIT_ADDRACK --------------------------
The WAIT_SINGLE_ADDRACK case is the one I am using. I have burst support
turned off in the DDR SDRAM core. The WAIT_LAST_ADDRACK case also has no
reference to OPB_retry. This may be a problem if you use the DDR SDRAM core
with burst mode enabled.

To date I have received no feedback from Xilinx developers to say the patch
I have implemented is correct or not. It does allow my system to operate,
and I have collected several gigabytes of data without error.

Regards,
Roger W. Cover
Spectral Instruments, Inc.
420 N. Bonita Ave.
Tucson, AZ 85745
Voice: 520-884-8821 ext. 144
FAX: 520-884-8803

-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx]On Behalf Of John
Williams
Sent: Monday, August 28, 2006 4:31 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] OPB DDR SDRAM controller locks the OPB
with multiple masters.


Hi Roger,

Roger W. Cover wrote:

> I have been working with the OPB DDR SDRAM controller with a bus-master
DMA
> unit in addition to the processor. I am writing to this list to provide
the
> community with the information I have discovered. The opb_ddr component in
> the EDK 8.1 hardware library has a bug in the ipic_pipe.vhd file.

[snip]

Thanks for the info and detailed explanation.

Would you be able to post your patch, so at least it will be recorded in the
archives?  I'm not sure if Xilinx have any plans for another service pack on
the
8.1 series tools, so it might be the only option until 8.2 is widely
adopted.

Thanks again,

John

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