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Re: [microblaze-uclinux] comunication between two microblazes on diferent fpga's



Doug, this is all very theoric yet, nothing is done. we are just studing ways of doing it. I like the idea of the shared RAM. And for the comunication MB - IP core, would you use the location of the data in a shared RAM or FSL?

On 9/7/06, Doug Gibbs <douggxlnx@xxxxxxxxx> wrote:
Nuno,
Is there any shared RAM between the two processors?
It would be much easier to communicate the location of the data,
instead of transferring the contents of a packet.
Doug

On 9/6/06, nuno pinto < nunomp@xxxxxxxxx> wrote:
> thank you christian, that's my idea!
>
> cheers
>
>
> On 9/6/06, Christian Schleiffer
> < christian.schleiffer@xxxxxxxxxxxxxxxxxx > wrote:
> > Hi,
> >
> > > I want to know if there is a way for two mb processors to comunicate
> > > even if they are on diferent fpga's connected.
> >
> > I remember a small university assignment where we had to connect two MBs
> > via FSL in
> > a single FPGA. Check Lab 3 on this page:
> > http://www.cs.lth.se/EDA380/labs.shtml
> >
> > Try to make that work and later on just add some custom hardware between
> > the FSL ports to transfer your data between the chips.
> >
> > Cheers
> > /Chris
> >
> > --
> > Christian Schleiffer
> > Communication Security (COSY)
> > Dept. of Electr. Eng. & Information Science
> > Ruhr-University Bochum, Germany
> > http://www.crypto.rub.de
> > cschleiffer@xxxxxxxxxxxxx
> > ___________________________
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> > microblaze-uclinux@xxxxxxxxxxxxxx
> > Project Home Page :
> http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> > Mailing List Archive :
> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
> >
> >
>
>
>
> --
> nuno pinto
> www.dei.isep.ipp.pt
> www.laboris.isep.ipp.pt
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nuno pinto
www.dei.isep.ipp.pt
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