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Hi, John, I did not use petalinux-copy-autoconfig and simply
download the image to SDRAM for execution. I will try to use petalinux-copy-autoconfig
and see if the design without DCACHE works. For the bootstrapping, will the build move entire code
itself from the flash to SDRAM, while the reset and exception vectors remain at
address zero in flash? Thanks & Best Regards, ************************************************************ Kevin Chen Xilinx - Embedded System Specialist Tel: +886-2-8176-1004 Fax:+886-2-2739-8423 Email: kevin.chen@xxxxxxxxxx Web: www.xilinx.com ************************************************************ -----Original Message----- Hi Kevin, Kevin Chen wrote: > My system has size limit. I can only have ICACHE,
without DCACHE, and > there will be NO LMB BRAM at address zero.
Instead, FLASH will be at > address zero and a bootloader will run from flash
and copy linux image > to SDRAM for execution. I am not sure if
Petalinux could be configured > in such a system? It's not an out-of-the-box configuration, but you can
certainly setup your system in this way. The tricky part about mapping flash to address 0x0
will be bootstrapping the system. MicroBlaze always jumps to 0x0 on
reset so you cannot even use EDK's bootloop mode to catch the CPU. At first thought your best approach may be to have two
hardware configurations, one with LMB mapped at zero, and use
this to load up the flash with interrupt/reset vectors, kernel image and
so on. Then boot into the real HW configuration with the flash mapped
at 0x0, and off you go. There's more to it than this, you'll need to tweak the
early bootup process in the kernel, for example. Look around
in arch/microblaze/kernel and arch/microblaze/platforms
for CONFIG_ROM - this is the closest existing thing to what you are
attempting. > I’ve tried to build a similar system
withour DCACHE, but with LMB BRAM > at address zero, it does not boot up and there is
no message showing on > UART console. As long as you do the necessary
petalinux-copy-autoconfig updates, that configuration should just work. Some more info
would be helpful - did you add FS-boot to your project, or download u-boot,
or directly load the kernel into SDRAM and execute it? Regards, John > System brief: > > Microblaze with ICACHE enable, DCACHE disable > > MCH_OPB_SDRAM: one XCL channel, OPB_IPIF enabled > > FLASH: (set to address 0 for Microblaze) > > UART > > No LMB BRAM (where IRQ and RESET vector resided
at address zero) > > > > Thanks > > -Kevin > > > ___________________________ microblaze-uclinux mailing list Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux Mailing List Archive :
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