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Re: [microblaze-uclinux] PetaLinux 0.20, including 2.6.20 kernel
Hi Mike,
Thanks for pointing this out. If you apply the attached patch it will
create the .template dir, and the problem should be resolved.
$ cd petalinux-v0.20-rc1
$ patch -p0 < petalinux-v0.20-template-fix.patch
I'll update the snapshot.
Thanks again,
John
Mike Dyer wrote:
> Hi,
>
> Just attempted to created a custom platform, and I get the following
> error:
>
> [mike@localhost petalinux-dist]$ petalinux-new-platform -v Provision -p
> PV2 -k 2.6
> cp: cannot stat `/home/mike/petalinux/software/petalinux-
> dist/linux-2.6.x/arch/microblaze/platform/.template': No such file or
> directory
> find: /home/mike/petalinux/software/petalinux-
> dist/linux-2.6.x/arch/microblaze/platform/Provision-PV2: No such file or
> directory
> awk: cmd. line:3: warning: escape sequence `\(' treated as plain `('
> awk: cmd. line:3: warning: escape sequence `\)' treated as plain `)'
> New platform for Provision PV2 successfully created
>
> I checked the tar file and the .template directory does seem to be
> missing...
>
> Cheers,
> Mike
>
>
> ___________________________
> microblaze-uclinux mailing list
> microblaze-uclinux@xxxxxxxxxxxxxx
> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>
Index: software/linux-2.6.x-petalogix/arch/microblaze/platform/.template/Kconfig.auto
===================================================================
--- software/linux-2.6.x-petalogix/arch/microblaze/platform/.template/Kconfig.auto (.../petalinux-v0.20-rc1) (revision 0)
+++ software/linux-2.6.x-petalogix/arch/microblaze/platform/.template/Kconfig.auto (.../petalinux-v0.20-rc2) (revision 2826)
@@ -0,0 +1,1754 @@
+############################################################
+#
+# CAUTION: This file is automatically generated by libgen.
+# EDK Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
+# Description: PetaLinux Configuration File - Kernel Version 2.6.x
+#
+############################################################
+
+
+# MAIN_MEMORY Settings
+comment "MAIN_MEMORY Settings"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_ERAM_START
+ hex "Start address of XILINX_ERAM" if ALLOW_EDIT_AUTO
+ default 0x22000000
+
+config XILINX_ERAM_SIZE
+ hex "Size of XILINX_ERAM" if ALLOW_EDIT_AUTO
+ default 0x02000000
+
+
+# FLASH_MEMORY Settings
+comment "FLASH_MEMORY Settings"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_FLASH_START
+ hex "Start address of XILINX_FLASH" if ALLOW_EDIT_AUTO
+ default 0x21000000
+
+config XILINX_FLASH_SIZE
+ hex "Size of XILINX_FLASH" if ALLOW_EDIT_AUTO
+ default 0x01000000
+
+config XILINX_FLASH_WIDTH
+ int "Bus width of XILINX_FLASH" if ALLOW_EDIT_AUTO
+ default 8
+
+config XILINX_FLASH_DATAWIDTH_MATCHING
+ int "Is datawidth matching enabled on this flash memory?" if ALLOW_EDIT_AUTO
+ default 1
+
+
+# LMB_MEMORY Settings
+comment "LMB_MEMORY Settings"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_LMB_START
+ hex "Start address of XILINX_LMB" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_LMB_SIZE
+ hex "Size of XILINX_LMB" if ALLOW_EDIT_AUTO
+ default 0x00004000
+
+
+# System Clock Frequency
+comment "System Clock Frequency"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_CPU_CLOCK_FREQ
+ int "System Clock Frequency (Hz)" if ALLOW_EDIT_AUTO
+ default 66666667
+
+
+# Definitions for MICROBLAZE0
+comment "Definitions for MICROBLAZE0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_MICROBLAZE0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default microblaze_0
+
+config XILINX_MICROBLAZE0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_MICROBLAZE0_INSTANCE
+ string "INSTANCE" if ALLOW_EDIT_AUTO
+ default microblaze_0
+
+config XILINX_MICROBLAZE0_D_OPB
+ int "D_OPB" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_D_LMB
+ int "D_LMB" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_I_OPB
+ int "I_OPB" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_I_LMB
+ int "I_LMB" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_USE_BARREL
+ int "USE_BARREL range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_USE_DIV
+ int "USE_DIV range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_USE_HW_MUL
+ int "USE_HW_MUL range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_USE_FPU
+ int "USE_FPU range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_USE_MSR_INSTR
+ int "USE_MSR_INSTR range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_USE_PCMP_INSTR
+ int "USE_PCMP_INSTR range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS
+ int "UNALIGNED_EXCEPTIONS range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION
+ int "ILL_OPCODE_EXCEPTION range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION
+ int "IOPB_BUS_EXCEPTION range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION
+ int "DOPB_BUS_EXCEPTION range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION
+ int "DIV_ZERO_EXCEPTION range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_FPU_EXCEPTION
+ int "FPU_EXCEPTION range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_DEBUG_ENABLED
+ int "DEBUG_ENABLED range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_NUMBER_OF_PC_BRK
+ int "NUMBER_OF_PC_BRK range (0:8)" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK
+ int "NUMBER_OF_RD_ADDR_BRK range (0:4)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK
+ int "NUMBER_OF_WR_ADDR_BRK range (0:4)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE
+ int "INTERRUPT_IS_EDGE range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MICROBLAZE0_EDGE_IS_POSITIVE
+ int "EDGE_IS_POSITIVE range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_FSL_LINKS
+ int "FSL_LINKS range (0:8)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_FSL_DATA_SIZE
+ int "FSL_DATA_SIZE range (1:32)" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_MICROBLAZE0_ICACHE_BASEADDR
+ hex "ICACHE_BASEADDR" if ALLOW_EDIT_AUTO
+ default 0x22000000
+
+config XILINX_MICROBLAZE0_ICACHE_HIGHADDR
+ hex "ICACHE_HIGHADDR" if ALLOW_EDIT_AUTO
+ default 0x23FFFFFF
+
+config XILINX_MICROBLAZE0_USE_ICACHE
+ int "USE_ICACHE range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_ALLOW_ICACHE_WR
+ int "ALLOW_ICACHE_WR range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_ADDR_TAG_BITS
+ int "ADDR_TAG_BITS range (0:23)" if ALLOW_EDIT_AUTO
+ default 12
+
+config XILINX_MICROBLAZE0_CACHE_BYTE_SIZE
+ int "CACHE_BYTE_SIZE range (1024,2048,4096,8192,16384,32768,65536)" if ALLOW_EDIT_AUTO
+ default 8192
+
+config XILINX_MICROBLAZE0_ICACHE_USE_FSL
+ int "ICACHE_USE_FSL range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_DCACHE_BASEADDR
+ hex "DCACHE_BASEADDR" if ALLOW_EDIT_AUTO
+ default 0x22000000
+
+config XILINX_MICROBLAZE0_DCACHE_HIGHADDR
+ hex "DCACHE_HIGHADDR" if ALLOW_EDIT_AUTO
+ default 0x23FFFFFF
+
+config XILINX_MICROBLAZE0_USE_DCACHE
+ int "USE_DCACHE range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_ALLOW_DCACHE_WR
+ int "ALLOW_DCACHE_WR range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_DCACHE_ADDR_TAG
+ int "DCACHE_ADDR_TAG range (0:21)" if ALLOW_EDIT_AUTO
+ default 12
+
+config XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE
+ int "DCACHE_BYTE_SIZE range (2048,4096,8192,16384,32768,65536)" if ALLOW_EDIT_AUTO
+ default 8192
+
+config XILINX_MICROBLAZE0_DCACHE_USE_FSL
+ int "DCACHE_USE_FSL range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MICROBLAZE0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default microblaze_0
+
+config XILINX_MICROBLAZE0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 4.00.a
+
+
+# Definitions for LMB_BRAM_IF_CNTLR_0
+comment "Definitions for LMB_BRAM_IF_CNTLR_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default dlmb_cntlr
+
+config XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x00003FFF
+
+config XILINX_LMB_BRAM_IF_CNTLR_0_MASK
+ hex "MASK" if ALLOW_EDIT_AUTO
+ default 0x034E0000
+
+config XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH
+ int "LMB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH
+ int "LMB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default dlmb_cntlr
+
+config XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 1.00.b
+
+
+# Definitions for LMB_BRAM_IF_CNTLR_1
+comment "Definitions for LMB_BRAM_IF_CNTLR_1"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default ilmb_cntlr
+
+config XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x00003FFF
+
+config XILINX_LMB_BRAM_IF_CNTLR_1_MASK
+ hex "MASK" if ALLOW_EDIT_AUTO
+ default 0x034E0000
+
+config XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH
+ int "LMB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH
+ int "LMB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default ilmb_cntlr
+
+config XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 1.00.b
+
+
+# Definitions for V20_0
+comment "Definitions for V20_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_V20_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default mb_opb
+
+config XILINX_V20_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_V20_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_V20_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_V20_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_V20_0_NUM_MASTERS
+ int "NUM_MASTERS" if ALLOW_EDIT_AUTO
+ default 3
+
+config XILINX_V20_0_NUM_SLAVES
+ int "NUM_SLAVES" if ALLOW_EDIT_AUTO
+ default 12
+
+config XILINX_V20_0_USE_LUT_OR
+ int "USE_LUT_OR range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_V20_0_EXT_RESET_HIGH
+ int "EXT_RESET_HIGH range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_V20_0_DYNAM_PRIORITY
+ int "DYNAM_PRIORITY range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_V20_0_PARK
+ int "PARK range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_V20_0_PROC_INTRFCE
+ int "PROC_INTRFCE range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_V20_0_REG_GRANTS
+ int "REG_GRANTS range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_V20_0_DEV_BLK_ID
+ int "DEV_BLK_ID range (0:255)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_V20_0_DEV_MIR_ENABLE
+ int "DEV_MIR_ENABLE range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_V20_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default mb_opb
+
+config XILINX_V20_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 1.10.c
+
+
+# Definitions for MDM_0
+comment "Definitions for MDM_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_MDM_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default debug_module
+
+config XILINX_MDM_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x41400000
+
+config XILINX_MDM_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x4140FFFF
+
+config XILINX_MDM_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_MDM_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_MDM_0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_MDM_0_MB_DBG_PORTS
+ int "MB_DBG_PORTS range (0:8)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MDM_0_USE_UART
+ int "USE_UART range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MDM_0_UART_WIDTH
+ int "UART_WIDTH range (8,16,32)" if ALLOW_EDIT_AUTO
+ default 8
+
+config XILINX_MDM_0_WRITE_FSL_PORTS
+ int "WRITE_FSL_PORTS range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MDM_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default debug_module
+
+config XILINX_MDM_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 2.00.a
+
+config XILINX_MDM_0_IRQ
+ int "IRQ number of MDM_0" if ALLOW_EDIT_AUTO
+ default 4
+
+
+# Definitions for UARTLITE_0
+comment "Definitions for UARTLITE_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_UARTLITE_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default RS232_DTE
+
+config XILINX_UARTLITE_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x40600000
+
+config XILINX_UARTLITE_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x4060FFFF
+
+config XILINX_UARTLITE_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_UARTLITE_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_UARTLITE_0_DATA_BITS
+ int "Num Data Bits" if ALLOW_EDIT_AUTO
+ default 8
+
+config XILINX_UARTLITE_0_CLK_FREQ
+ int "CLK_FREQ" if ALLOW_EDIT_AUTO
+ default 66666667
+
+config XILINX_UARTLITE_0_BAUDRATE
+ int "Baudrate" if ALLOW_EDIT_AUTO
+ default 115200
+
+config XILINX_UARTLITE_0_USE_PARITY
+ int "Use Parity" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_UARTLITE_0_ODD_PARITY
+ int "Parity Type" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_UARTLITE_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default RS232_DTE
+
+config XILINX_UARTLITE_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 1.00.b
+
+config XILINX_UARTLITE_0_IRQ
+ int "IRQ number of UARTLITE_0" if ALLOW_EDIT_AUTO
+ default 2
+
+
+# Definitions for GPIO_0
+comment "Definitions for GPIO_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_GPIO_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default LEDs_8Bit
+
+config XILINX_GPIO_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x40040000
+
+config XILINX_GPIO_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x4004FFFF
+
+config XILINX_GPIO_0_USER_ID_CODE
+ int "USER_ID_CODE range (0:255)" if ALLOW_EDIT_AUTO
+ default 3
+
+config XILINX_GPIO_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_GPIO_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_GPIO_0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_GPIO_0_GPIO_WIDTH
+ int "GPIO Data Width" if ALLOW_EDIT_AUTO
+ default 8
+
+config XILINX_GPIO_0_ALL_INPUTS
+ int "Data pins are all inputs" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_GPIO_0_INTERRUPT_PRESENT
+ int "INTERRUPT_PRESENT range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_GPIO_0_IS_BIDIR
+ int "Data pins are bi-directional" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_GPIO_0_DOUT_DEFAULT
+ hex "DOUT_DEFAULT" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_GPIO_0_TRI_DEFAULT
+ hex "TRI_DEFAULT" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_GPIO_0_IS_DUAL
+ int "Use Dual GPIO" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_GPIO_0_ALL_INPUTS_2
+ int "GPIO2 Data All Inputs" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_GPIO_0_IS_BIDIR_2
+ int "Use GPIO2 Bidir IO Pin" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_GPIO_0_DOUT_DEFAULT_2
+ hex "DOUT_DEFAULT_2" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_GPIO_0_TRI_DEFAULT_2
+ hex "TRI_DEFAULT_2" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_GPIO_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default LEDs_8Bit
+
+config XILINX_GPIO_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 3.01.b
+
+
+# Definitions for GPIO_1
+comment "Definitions for GPIO_1"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_GPIO_1_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default DIP_Switches_4Bit
+
+config XILINX_GPIO_1_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x40060000
+
+config XILINX_GPIO_1_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x4006FFFF
+
+config XILINX_GPIO_1_USER_ID_CODE
+ int "USER_ID_CODE range (0:255)" if ALLOW_EDIT_AUTO
+ default 3
+
+config XILINX_GPIO_1_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_GPIO_1_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_GPIO_1_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_GPIO_1_GPIO_WIDTH
+ int "GPIO Data Width" if ALLOW_EDIT_AUTO
+ default 4
+
+config XILINX_GPIO_1_ALL_INPUTS
+ int "Data pins are all inputs" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_GPIO_1_INTERRUPT_PRESENT
+ int "INTERRUPT_PRESENT range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_GPIO_1_IS_BIDIR
+ int "Data pins are bi-directional" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_GPIO_1_DOUT_DEFAULT
+ hex "DOUT_DEFAULT" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_GPIO_1_TRI_DEFAULT
+ hex "TRI_DEFAULT" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_GPIO_1_IS_DUAL
+ int "Use Dual GPIO" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_GPIO_1_ALL_INPUTS_2
+ int "GPIO2 Data All Inputs" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_GPIO_1_IS_BIDIR_2
+ int "Use GPIO2 Bidir IO Pin" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_GPIO_1_DOUT_DEFAULT_2
+ hex "DOUT_DEFAULT_2" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_GPIO_1_TRI_DEFAULT_2
+ hex "TRI_DEFAULT_2" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_GPIO_1_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default DIP_Switches_4Bit
+
+config XILINX_GPIO_1_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 3.01.b
+
+
+# Definitions for LCD_2X16_0
+comment "Definitions for LCD_2X16_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_LCD_2X16_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default Character_LCD_2x16
+
+config XILINX_LCD_2X16_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x40080000
+
+config XILINX_LCD_2X16_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x4008FFFF
+
+config XILINX_LCD_2X16_0_USER_ID_CODE
+ int "USER_ID_CODE range (0:255)" if ALLOW_EDIT_AUTO
+ default 3
+
+config XILINX_LCD_2X16_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_LCD_2X16_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_LCD_2X16_0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_LCD_2X16_0_GPIO_WIDTH
+ int "GPIO Data Width" if ALLOW_EDIT_AUTO
+ default 7
+
+config XILINX_LCD_2X16_0_ALL_INPUTS
+ int "Data pins are all inputs" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_LCD_2X16_0_INTERRUPT_PRESENT
+ int "INTERRUPT_PRESENT range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_LCD_2X16_0_IS_BIDIR
+ int "Data pins are bi-directional" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_LCD_2X16_0_DOUT_DEFAULT
+ hex "DOUT_DEFAULT" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_LCD_2X16_0_TRI_DEFAULT
+ hex "TRI_DEFAULT" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_LCD_2X16_0_IS_DUAL
+ int "Use Dual GPIO" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_LCD_2X16_0_ALL_INPUTS_2
+ int "GPIO2 Data All Inputs" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_LCD_2X16_0_IS_BIDIR_2
+ int "Use GPIO2 Bidir IO Pin" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_LCD_2X16_0_DOUT_DEFAULT_2
+ hex "DOUT_DEFAULT_2" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_LCD_2X16_0_TRI_DEFAULT_2
+ hex "TRI_DEFAULT_2" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_LCD_2X16_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default Character_LCD_2x16
+
+config XILINX_LCD_2X16_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 3.01.b
+
+
+# Definitions for SOFT_RESET_0
+comment "Definitions for SOFT_RESET_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_SOFT_RESET_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default Reset_GPIO
+
+config XILINX_SOFT_RESET_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x40020000
+
+config XILINX_SOFT_RESET_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x4002FFFF
+
+config XILINX_SOFT_RESET_0_USER_ID_CODE
+ int "USER_ID_CODE range (0:255)" if ALLOW_EDIT_AUTO
+ default 3
+
+config XILINX_SOFT_RESET_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_SOFT_RESET_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_SOFT_RESET_0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_SOFT_RESET_0_GPIO_WIDTH
+ int "GPIO Data Width" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_SOFT_RESET_0_ALL_INPUTS
+ int "Data pins are all inputs" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_SOFT_RESET_0_INTERRUPT_PRESENT
+ int "INTERRUPT_PRESENT range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_SOFT_RESET_0_IS_BIDIR
+ int "Data pins are bi-directional" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_SOFT_RESET_0_DOUT_DEFAULT
+ hex "DOUT_DEFAULT" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_SOFT_RESET_0_TRI_DEFAULT
+ hex "TRI_DEFAULT" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_SOFT_RESET_0_IS_DUAL
+ int "Use Dual GPIO" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_SOFT_RESET_0_ALL_INPUTS_2
+ int "GPIO2 Data All Inputs" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_SOFT_RESET_0_IS_BIDIR_2
+ int "Use GPIO2 Bidir IO Pin" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_SOFT_RESET_0_DOUT_DEFAULT_2
+ hex "DOUT_DEFAULT_2" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_SOFT_RESET_0_TRI_DEFAULT_2
+ hex "TRI_DEFAULT_2" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_SOFT_RESET_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default Reset_GPIO
+
+config XILINX_SOFT_RESET_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 3.01.b
+
+
+# Definitions for BTN_DECODER_0
+comment "Definitions for BTN_DECODER_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_BTN_DECODER_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default btn_rotary_decoder
+
+config XILINX_BTN_DECODER_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x400A0000
+
+config XILINX_BTN_DECODER_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x400AFFFF
+
+config XILINX_BTN_DECODER_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_BTN_DECODER_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_BTN_DECODER_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default btn_rotary_decoder
+
+config XILINX_BTN_DECODER_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 1.00.a
+
+config XILINX_BTN_DECODER_0_IRQ
+ int "IRQ number of BTN_DECODER_0" if ALLOW_EDIT_AUTO
+ default 3
+
+
+# Definitions for EMC_0
+comment "Definitions for EMC_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_EMC_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default FLASH_16Mx8
+
+config XILINX_EMC_0_NUM_BANKS_MEM
+ int "NUM_BANKS_MEM range (1:4)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_EMC_0_INCLUDE_BURST
+ int "INCLUDE_BURST range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_EMC_0_INCLUDE_NEGEDGE_IOREGS
+ int "INCLUDE_NEGEDGE_IOREGS range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_EMC_0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_EMC_0_MEM0_BASEADDR
+ hex "Bank 0 Base Address" if ALLOW_EDIT_AUTO
+ default 0x21000000
+
+config XILINX_EMC_0_MEM0_HIGHADDR
+ hex "Bank 0 High Address" if ALLOW_EDIT_AUTO
+ default 0x21FFFFFF
+
+config XILINX_EMC_0_MEM1_BASEADDR
+ hex "Bank 1 Base Address" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_EMC_0_MEM1_HIGHADDR
+ hex "Bank 1 High Address" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_EMC_0_MEM2_BASEADDR
+ hex "Bank 2 Base Address" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_EMC_0_MEM2_HIGHADDR
+ hex "Bank 2 High Address" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_EMC_0_MEM3_BASEADDR
+ hex "Bank 3 Base Address" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_EMC_0_MEM3_HIGHADDR
+ hex "Bank 3 High Address" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_EMC_0_MEM0_WIDTH
+ int "Data Width" if ALLOW_EDIT_AUTO
+ default 8
+
+config XILINX_EMC_0_MEM1_WIDTH
+ int "Bank 1 Data Bus Width" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_EMC_0_MEM2_WIDTH
+ int "Bank 2 Data Bus Width" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_EMC_0_MEM3_WIDTH
+ int "Bank 3 Data Bus Width" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_EMC_0_MAX_MEM_WIDTH
+ int "Maximum Data Width" if ALLOW_EDIT_AUTO
+ default 8
+
+config XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_0
+ int "Match width of memory data bus to OPB data bus" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_1
+ int "Match data bus width of Mem Bank 1 to OPB" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_2
+ int "Match data bus width of Mem Bank 2 to OPB" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_3
+ int "Match data bus width of Mem Bank 3 to OPB" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_EMC_0_SYNCH_MEM_0
+ int "Memory Type" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_EMC_0_SYNCH_PIPEDELAY_0
+ int "SYNCH_PIPEDELAY_0 range (1:2)" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_EMC_0_TCEDV_PS_MEM_0
+ int "TCEDV_PS_MEM_0" if ALLOW_EDIT_AUTO
+ default 110000
+
+config XILINX_EMC_0_TAVDV_PS_MEM_0
+ int "TAVDV_PS_MEM_0" if ALLOW_EDIT_AUTO
+ default 110000
+
+config XILINX_EMC_0_THZCE_PS_MEM_0
+ int "THZCE_PS_MEM_0" if ALLOW_EDIT_AUTO
+ default 35000
+
+config XILINX_EMC_0_THZOE_PS_MEM_0
+ int "THZOE_PS_MEM_0" if ALLOW_EDIT_AUTO
+ default 7000
+
+config XILINX_EMC_0_TWC_PS_MEM_0
+ int "TWC_PS_MEM_0" if ALLOW_EDIT_AUTO
+ default 110000
+
+config XILINX_EMC_0_TWP_PS_MEM_0
+ int "TWP_PS_MEM_0" if ALLOW_EDIT_AUTO
+ default 70000
+
+config XILINX_EMC_0_TLZWE_PS_MEM_0
+ int "TLZWE_PS_MEM_0" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_SYNCH_MEM_1
+ int "SYNCH_MEM_1 range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_EMC_0_SYNCH_PIPEDELAY_1
+ int "SYNCH_PIPEDELAY_1 range (1:2)" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_EMC_0_TCEDV_PS_MEM_1
+ int "TCEDV_PS_MEM_1" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_TAVDV_PS_MEM_1
+ int "TAVDV_PS_MEM_1" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_THZCE_PS_MEM_1
+ int "THZCE_PS_MEM_1" if ALLOW_EDIT_AUTO
+ default 7000
+
+config XILINX_EMC_0_THZOE_PS_MEM_1
+ int "THZOE_PS_MEM_1" if ALLOW_EDIT_AUTO
+ default 7000
+
+config XILINX_EMC_0_TWC_PS_MEM_1
+ int "TWC_PS_MEM_1" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_TWP_PS_MEM_1
+ int "TWP_PS_MEM_1" if ALLOW_EDIT_AUTO
+ default 12000
+
+config XILINX_EMC_0_TLZWE_PS_MEM_1
+ int "TLZWE_PS_MEM_1" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_EMC_0_SYNCH_MEM_2
+ int "SYNCH_MEM_2 range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_EMC_0_SYNCH_PIPEDELAY_2
+ int "SYNCH_PIPEDELAY_2 range (1:2)" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_EMC_0_TCEDV_PS_MEM_2
+ int "TCEDV_PS_MEM_2" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_TAVDV_PS_MEM_2
+ int "TAVDV_PS_MEM_2" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_THZCE_PS_MEM_2
+ int "THZCE_PS_MEM_2" if ALLOW_EDIT_AUTO
+ default 7000
+
+config XILINX_EMC_0_THZOE_PS_MEM_2
+ int "THZOE_PS_MEM_2" if ALLOW_EDIT_AUTO
+ default 7000
+
+config XILINX_EMC_0_TWC_PS_MEM_2
+ int "TWC_PS_MEM_2" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_TWP_PS_MEM_2
+ int "TWP_PS_MEM_2" if ALLOW_EDIT_AUTO
+ default 12000
+
+config XILINX_EMC_0_TLZWE_PS_MEM_2
+ int "TLZWE_PS_MEM_2" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_EMC_0_SYNCH_MEM_3
+ int "SYNCH_MEM_3 range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_EMC_0_SYNCH_PIPEDELAY_3
+ int "SYNCH_PIPEDELAY_3 range (1:2)" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_EMC_0_TCEDV_PS_MEM_3
+ int "TCEDV_PS_MEM_3" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_TAVDV_PS_MEM_3
+ int "TAVDV_PS_MEM_3" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_THZCE_PS_MEM_3
+ int "THZCE_PS_MEM_3" if ALLOW_EDIT_AUTO
+ default 7000
+
+config XILINX_EMC_0_THZOE_PS_MEM_3
+ int "THZOE_PS_MEM_3" if ALLOW_EDIT_AUTO
+ default 7000
+
+config XILINX_EMC_0_TWC_PS_MEM_3
+ int "TWC_PS_MEM_3" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_EMC_0_TWP_PS_MEM_3
+ int "TWP_PS_MEM_3" if ALLOW_EDIT_AUTO
+ default 12000
+
+config XILINX_EMC_0_TLZWE_PS_MEM_3
+ int "TLZWE_PS_MEM_3" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_EMC_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_EMC_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_EMC_0_OPB_CLK_PERIOD_PS
+ int "OPB_CLK_PERIOD_PS" if ALLOW_EDIT_AUTO
+ default 14999
+
+config XILINX_EMC_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default FLASH_16Mx8
+
+config XILINX_EMC_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 2.00.a
+
+
+# Definitions for MCH_OPB_DDR_0
+comment "Definitions for MCH_OPB_DDR_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_MCH_OPB_DDR_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default DDR_SDRAM_32Mx16
+
+config XILINX_MCH_OPB_DDR_0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_MCH_OPB_DDR_0_REG_DIMM
+ int "DDR device is a registerd DIMM" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_NUM_BANKS_MEM
+ int "NUM_BANKS_MEM range (1:4)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_NUM_CLK_PAIRS
+ int "NUM_CLK_PAIRS range (1:4)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_DDR_ASYNC_SUPPORT
+ int "Separate DDR and bus clock domain" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_EXTRA_TSU
+ int "EXTRA_TSU range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_USE_OPEN_ROW_MNGT
+ int "USE_OPEN_ROW_MNGT range (0:1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_INCLUDE_DDR_PIPE
+ int "INCLUDE_DDR_PIPE range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_NUM_CHANNELS
+ int "NUM_CHANNELS range (1:4)" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_MCH_OPB_DDR_0_PRIORITY_MODE
+ int "PRIORITY_MODE" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_IPIF
+ int "INCLUDE_OPB_IPIF range (0:1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_BURST_SUPPORT
+ int "Include Burst Transactions Support" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_INCLUDE_TIMEOUT_CNTR
+ int "INCLUDE_TIMEOUT_CNTR range (0)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_TIMEOUT
+ int "TIMEOUT range (1:512)" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_MCH_OPB_DWIDTH
+ int "MCH_OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_MCH_OPB_DDR_0_MCH_OPB_AWIDTH
+ int "MCH_OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_MCH_OPB_DDR_0_MCH_OPB_CLK_PERIOD_PS
+ int "MCH_OPB_CLK_PERIOD_PS" if ALLOW_EDIT_AUTO
+ default 14999
+
+config XILINX_MCH_OPB_DDR_0_DDR_TMRD
+ int "DDR_TMRD" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_MCH_OPB_DDR_0_DDR_TWR
+ int "DDR_TWR" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_MCH_OPB_DDR_0_DDR_TWTR
+ int "DDR_TWTR" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_DDR_TRAS
+ int "DDR_TRAS" if ALLOW_EDIT_AUTO
+ default 40000
+
+config XILINX_MCH_OPB_DDR_0_DDR_TRC
+ int "DDR_TRC" if ALLOW_EDIT_AUTO
+ default 65000
+
+config XILINX_MCH_OPB_DDR_0_DDR_TRFC
+ int "DDR_TRFC" if ALLOW_EDIT_AUTO
+ default 75000
+
+config XILINX_MCH_OPB_DDR_0_DDR_TRCD
+ int "DDR_TRCD" if ALLOW_EDIT_AUTO
+ default 20000
+
+config XILINX_MCH_OPB_DDR_0_DDR_TRRD
+ int "DDR_TRRD" if ALLOW_EDIT_AUTO
+ default 15000
+
+config XILINX_MCH_OPB_DDR_0_DDR_TREFI
+ int "DDR_TREFI" if ALLOW_EDIT_AUTO
+ default 7800000
+
+config XILINX_MCH_OPB_DDR_0_DDR_TRP
+ int "DDR_TRP" if ALLOW_EDIT_AUTO
+ default 20000
+
+config XILINX_MCH_OPB_DDR_0_DDR_TXSR
+ int "DDR_TXSR" if ALLOW_EDIT_AUTO
+ default 80000
+
+config XILINX_MCH_OPB_DDR_0_DDR_CAS_LAT
+ int "DDR_CAS_LAT range (2,3)" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_MCH_OPB_DDR_0_DDR_DWIDTH
+ int "Data Width" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_DDR_AWIDTH
+ int "Address Width" if ALLOW_EDIT_AUTO
+ default 13
+
+config XILINX_MCH_OPB_DDR_0_DDR_COL_AWIDTH
+ int "Column Address Width" if ALLOW_EDIT_AUTO
+ default 10
+
+config XILINX_MCH_OPB_DDR_0_DDR_BANK_AWIDTH
+ int "Bank Address Width" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_MCH_OPB_DDR_0_MCH0_PROTOCOL
+ int "MCH0_PROTOCOL" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_MCH0_ACCESSBUF_DEPTH
+ int "MCH0_ACCESSBUF_DEPTH range (4,8,16)" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_MCH0_RDDATABUF_DEPTH
+ int "MCH0_RDDATABUF_DEPTH range (0,4,8,16)" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_MCH1_PROTOCOL
+ int "MCH1_PROTOCOL" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_MCH1_ACCESSBUF_DEPTH
+ int "MCH1_ACCESSBUF_DEPTH range (4,8,16)" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_MCH1_RDDATABUF_DEPTH
+ int "MCH1_RDDATABUF_DEPTH range (0,4,8,16)" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_MCH2_PROTOCOL
+ int "MCH2_PROTOCOL" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_MCH2_ACCESSBUF_DEPTH
+ int "MCH2_ACCESSBUF_DEPTH range (4,8,16)" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_MCH2_RDDATABUF_DEPTH
+ int "MCH2_RDDATABUF_DEPTH range (0,4,8,16)" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_MCH3_PROTOCOL
+ int "MCH3_PROTOCOL" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_MCH_OPB_DDR_0_MCH3_ACCESSBUF_DEPTH
+ int "MCH3_ACCESSBUF_DEPTH range (4,8,16)" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_MCH3_RDDATABUF_DEPTH
+ int "MCH3_RDDATABUF_DEPTH range (0,4,8,16)" if ALLOW_EDIT_AUTO
+ default 16
+
+config XILINX_MCH_OPB_DDR_0_XCL0_LINESIZE
+ int "XCL0_LINESIZE range (1,4,8,16)" if ALLOW_EDIT_AUTO
+ default 4
+
+config XILINX_MCH_OPB_DDR_0_XCL0_WRITEXFER
+ int "XCL0_WRITEXFER range (0:2)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_XCL1_LINESIZE
+ int "XCL1_LINESIZE range (1,4,8,16)" if ALLOW_EDIT_AUTO
+ default 4
+
+config XILINX_MCH_OPB_DDR_0_XCL1_WRITEXFER
+ int "XCL1_WRITEXFER range (0:2)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_XCL2_LINESIZE
+ int "XCL2_LINESIZE range (1,4,8,16)" if ALLOW_EDIT_AUTO
+ default 4
+
+config XILINX_MCH_OPB_DDR_0_XCL2_WRITEXFER
+ int "XCL2_WRITEXFER range (0:2)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_XCL3_LINESIZE
+ int "XCL3_LINESIZE range (1,4,8,16)" if ALLOW_EDIT_AUTO
+ default 4
+
+config XILINX_MCH_OPB_DDR_0_XCL3_WRITEXFER
+ int "XCL3_WRITEXFER range (0:2)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_0_MEM0_BASEADDR
+ hex "Bank 0 Base Address" if ALLOW_EDIT_AUTO
+ default 0x22000000
+
+config XILINX_MCH_OPB_DDR_0_MEM0_HIGHADDR
+ hex "Bank 0 High Address" if ALLOW_EDIT_AUTO
+ default 0x23FFFFFF
+
+config XILINX_MCH_OPB_DDR_0_MEM1_BASEADDR
+ hex "MEM1_BASEADDR" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_MCH_OPB_DDR_0_MEM1_HIGHADDR
+ hex "MEM1_HIGHADDR" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_MCH_OPB_DDR_0_MEM2_BASEADDR
+ hex "MEM2_BASEADDR" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_MCH_OPB_DDR_0_MEM2_HIGHADDR
+ hex "MEM2_HIGHADDR" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_MCH_OPB_DDR_0_MEM3_BASEADDR
+ hex "MEM3_BASEADDR" if ALLOW_EDIT_AUTO
+ default 0xFFFFFFFF
+
+config XILINX_MCH_OPB_DDR_0_MEM3_HIGHADDR
+ hex "MEM3_HIGHADDR" if ALLOW_EDIT_AUTO
+ default 0x00000000
+
+config XILINX_MCH_OPB_DDR_0_SIM_INIT_TIME_PS
+ int "SIM_INIT_TIME_PS" if ALLOW_EDIT_AUTO
+ default 100000000
+
+config XILINX_MCH_OPB_DDR_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default DDR_SDRAM_32Mx16
+
+config XILINX_MCH_OPB_DDR_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 1.00.b
+
+
+# Definitions for ETHERNET_0
+comment "Definitions for ETHERNET_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_ETHERNET_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default Ethernet_MAC
+
+config XILINX_ETHERNET_0_DEV_BLK_ID
+ int "DEV_BLK_ID range (0:255)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_DEV_MIR_ENABLE
+ int "DEV_MIR_ENABLE range (0:255)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x40C00000
+
+config XILINX_ETHERNET_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x40C0FFFF
+
+config XILINX_ETHERNET_0_RESET_PRESENT
+ int "RESET_PRESENT range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER
+ int "INCLUDE_DEV_PENCODER range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_DMA_PRESENT
+ int "DMA Present" if ALLOW_EDIT_AUTO
+ default 3
+
+config XILINX_ETHERNET_0_DMA_INTR_COALESCE
+ int "DMA_INTR_COALESCE range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_ETHERNET_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS
+ int "OPB_CLK_PERIOD_PS" if ALLOW_EDIT_AUTO
+ default 14999
+
+config XILINX_ETHERNET_0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_ETHERNET_0_IPIF_RDFIFO_DEPTH
+ int "IPIF READ FIFO DEPTH" if ALLOW_EDIT_AUTO
+ default 32768
+
+config XILINX_ETHERNET_0_IPIF_WRFIFO_DEPTH
+ int "IPIF WRITE FIFO DEPTH" if ALLOW_EDIT_AUTO
+ default 32768
+
+config XILINX_ETHERNET_0_MIIM_CLKDVD
+ hex "MIIM_CLKDVD" if ALLOW_EDIT_AUTO
+ default 0x0000001F
+
+config XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST
+ int "SOURCE_ADDR_INSERT_EXIST" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_PAD_INSERT_EXIST
+ int "PAD_INSERT_EXIST" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_FCS_INSERT_EXIST
+ int "FCS_INSERT_EXIST" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_MAC_FIFO_DEPTH
+ int "MAC_FIFO_DEPTH range (16,32,64)" if ALLOW_EDIT_AUTO
+ default 64
+
+config XILINX_ETHERNET_0_MAC_FIFO_BRAM_1_SRL_0
+ int "MAC_FIFO_BRAM_1_SRL_0 range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_ETHERNET_0_HALF_DUPLEX_EXIST
+ int "HALF_DUPLEX_EXIST range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_ERR_COUNT_EXIST
+ int "ERR_COUNT_EXIST" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_CAM_EXIST
+ int "CAM_EXIST range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_ETHERNET_0_CAM_BRAM_0_SRL_1
+ int "CAM_BRAM_0_SRL_1 range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_JUMBO_EXIST
+ int "JUMBO_EXIST range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_ETHERNET_0_MII_EXIST
+ int "MII_EXIST" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_ETHERNET_0_TX_DRE_TYPE
+ int "TX_DRE_TYPE range (0:2)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_ETHERNET_0_RX_DRE_TYPE
+ int "RX_DRE_TYPE range (0:2)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_ETHERNET_0_TX_INCLUDE_CSUM
+ int "TX_INCLUDE_CSUM range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_ETHERNET_0_RX_INCLUDE_CSUM
+ int "RX_INCLUDE_CSUM range (0,1)" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_ETHERNET_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default Ethernet_MAC
+
+config XILINX_ETHERNET_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 1.04.a
+
+config XILINX_ETHERNET_0_IRQ
+ int "IRQ number of ETHERNET_0" if ALLOW_EDIT_AUTO
+ default 1
+
+
+# Definitions for TIMER_0
+comment "Definitions for TIMER_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_TIMER_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default opb_timer_0
+
+config XILINX_TIMER_0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_TIMER_0_COUNT_WIDTH
+ int "Counter Bit Width" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_TIMER_0_ONE_TIMER_ONLY
+ int "Timer Mode" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_TIMER_0_TRIG0_ASSERT
+ int "TRIG0_ASSERT range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_TIMER_0_TRIG1_ASSERT
+ int "TRIG1_ASSERT range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_TIMER_0_GEN0_ASSERT
+ int "GEN0_ASSERT range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_TIMER_0_GEN1_ASSERT
+ int "GEN1_ASSERT range (0,1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_TIMER_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_TIMER_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_TIMER_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x41C00000
+
+config XILINX_TIMER_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x41C0FFFF
+
+config XILINX_TIMER_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default opb_timer_0
+
+config XILINX_TIMER_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 1.00.b
+
+config XILINX_TIMER_0_IRQ
+ int "IRQ number of TIMER_0" if ALLOW_EDIT_AUTO
+ default 0
+
+
+# Definitions for INTC_0
+comment "Definitions for INTC_0"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_INTC_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default opb_intc_0
+
+config XILINX_INTC_0_FAMILY
+ string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+ default spartan3e
+
+config XILINX_INTC_0_Y
+ int "Y" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_INTC_0_X
+ int "X" if ALLOW_EDIT_AUTO
+ default 0
+
+config XILINX_INTC_0_U_SET
+ string "U_SET" if ALLOW_EDIT_AUTO
+ default intc
+
+config XILINX_INTC_0_OPB_AWIDTH
+ int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_INTC_0_OPB_DWIDTH
+ int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
+ default 32
+
+config XILINX_INTC_0_BASEADDR
+ hex "Base address" if ALLOW_EDIT_AUTO
+ default 0x41200000
+
+config XILINX_INTC_0_HIGHADDR
+ hex "High address" if ALLOW_EDIT_AUTO
+ default 0x4120FFFF
+
+config XILINX_INTC_0_NUM_INTR_INPUTS
+ int "NUM_INTR_INPUTS range (1:C_OPB_DWIDTH)" if ALLOW_EDIT_AUTO
+ default 5
+
+config XILINX_INTC_0_KIND_OF_INTR
+ hex "KIND_OF_INTR" if ALLOW_EDIT_AUTO
+ default 0x00000014
+
+config XILINX_INTC_0_KIND_OF_EDGE
+ hex "KIND_OF_EDGE" if ALLOW_EDIT_AUTO
+ default 0x00000014
+
+config XILINX_INTC_0_KIND_OF_LVL
+ hex "KIND_OF_LVL" if ALLOW_EDIT_AUTO
+ default 0x0000000B
+
+config XILINX_INTC_0_HAS_IPR
+ int "Interrupt Pending Register" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_INTC_0_HAS_SIE
+ int "Set Interrupt Enables" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_INTC_0_HAS_CIE
+ int "Clear Interrupt Enables" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_INTC_0_HAS_IVR
+ int "Interrupt Vector Register" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_INTC_0_IRQ_IS_LEVEL
+ int "IRQ_IS_LEVEL range (0, 1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_INTC_0_IRQ_ACTIVE
+ int "IRQ_ACTIVE range (0, 1)" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_INTC_0_INSTANCE
+ string "Core Instance Name" if ALLOW_EDIT_AUTO
+ default opb_intc_0
+
+config XILINX_INTC_0_HW_VER
+ string "Core version number" if ALLOW_EDIT_AUTO
+ default 1.00.c
+
+
+# Peripheral counts
+comment "Peripheral counts"
+ depends on ALLOW_EDIT_AUTO
+
+config XILINX_TIMER_NUM_INSTANCES
+ int "Number of TIMER instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_UARTLITE_NUM_INSTANCES
+ int "Number of UARTLITE instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES
+ int "Number of LMB_BRAM_IF_CNTLR instances" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_INTC_NUM_INSTANCES
+ int "Number of INTC instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_V20_NUM_INSTANCES
+ int "Number of V20 instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_BTN_DECODER_NUM_INSTANCES
+ int "Number of BTN_DECODER instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MCH_OPB_DDR_NUM_INSTANCES
+ int "Number of MCH_OPB_DDR instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_LCD_2X16_NUM_INSTANCES
+ int "Number of LCD_2X16 instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_EMC_NUM_INSTANCES
+ int "Number of EMC instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_MDM_NUM_INSTANCES
+ int "Number of MDM instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_SOFT_RESET_NUM_INSTANCES
+ int "Number of SOFT_RESET instances" if ALLOW_EDIT_AUTO
+ default 1
+
+config XILINX_GPIO_NUM_INSTANCES
+ int "Number of GPIO instances" if ALLOW_EDIT_AUTO
+ default 2
+
+config XILINX_ETHERNET_NUM_INSTANCES
+ int "Number of ETHERNET instances" if ALLOW_EDIT_AUTO
+ default 1
+
+
Index: software/linux-2.6.x-petalogix/arch/microblaze/platform/.template/Makefile
===================================================================
--- software/linux-2.6.x-petalogix/arch/microblaze/platform/.template/Makefile (.../petalinux-v0.20-rc1) (revision 0)
+++ software/linux-2.6.x-petalogix/arch/microblaze/platform/.template/Makefile (.../petalinux-v0.20-rc2) (revision 2826)
@@ -0,0 +1,5 @@
+#
+# Empty Makefile to keep make clean happy
+#
+
+