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Raul, Manufacturers place performance
specifications on their chips. The chips are then tested to make sure they at
least meet those specifications before they are shipped. A chip with timing on
the borderline but passes is shipped just the same as a chip that passes with
lots of extra room. For example, the datasheet may specify a setup time of 3ns.
An actual chip may only need 2.9 ns and another may only need 2.0 ns. Or, an
FPGA may be specified to run at 300 MHz for specific test case, whereas the
real chips may range from 300 to 400 MHz performance. Chips’
performances may vary which is why it is critical that your FPGA design be
properly constrained and then meets those constraints during implementation. Have you tried the memory test from Base
System Builder? By default, the TestApp_Memory only tests the 1st 4KB
of memory. I recommend you go into the code and increase the test scope to the
full memory size, which on the Spartan-3 MB board is 32MB. Then also put the
test in a loop so it keeps repeating itself. Capture the output from the
terminal to track any errors. Let it run overnight. If you still don’t
get any failures, then your problem below is not memory related. You can also email technical.support@xxxxxxxxx and provide the approximate ship dates for your working and
non-working boards and ask if there were any changes to the Bill of Materials
between those two builds. Otherwise, I’d contact your local
Avnet FAE and get some help directly from them. Regards, From: owner- Thanks for your answer What do you mean with
“being closer to their own specification borderline”? Regards, Raul Camaras -----Ursprüngliche
Nachricht----- Raul, If you
are referring to the Memec Spartan-3 MB board with XC3S1500, I don’t
believe there have been any changes. The boards are all tested before
customer shipment, but you can download the functional test and test it
yourself if you are suspicious about the board itself. You can get the
support files for all Avnet/Memec boards from www.em.avnet.com/drc. The specific
link for this board is: The
error below is indicative of a memory problem. I would test the DDR on
the board and then closely inspect the timing report for the design from which
your download.bit was generated. It is possible to have a marginal design
that works fine on one board and fails on another due to the FPGA and DDR chips
themselves being closer to their own specification borderline. Regards, From: owner- Hello, I just
received two new demo boards: Memec Spartan-3 development board. I download
FPGA program with EDK, I launch xmd, and I load successfully image.bin to RAM
with “dow –data …”. When I make
“con 0x22000000” to start uClinux xmd gives next error: XMD%dow
–data /tftpboot/image.bin 0x22000000 XMD%con
0x22000000 Processor
started. Type “stop” to stop processor. RUNNING> XMD% ERROR: MTD
– MicroBlaze Pipeline Stalled executing Instruction at >> PC:
0x2211eca4 Try Resetting
the Processor to Continue.. XMD% Strangely,
using the same FPGA program(download.bit) and image.bin on our old MEMEC
boards, it works! May they have
changed something on the board? Some help?
Thanks. Raul Camaras |