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[microblaze-uclinux] PetaLinux on XC3S1600E Digilent board
I'm trying to use the Digilent Xilinx Spartan3E-1600 board with the
reference design I downloaded from the petalinux website. I've tried
the 9.1 and 8.2 versions (using the appropriate versions of Xilinx
tools) put can not meet timing. Is there a trick I'm missing? I did
try inserting input buffers on the PHY tx and rx clocks (as was done in
the Avnet uClinux port), but that didn't help.
Thanks,
Jim
------------------------------------------------------------------------
------------------------------
Constraint | Requested | Actual |
Logic | Absolute |Number of
| | |
Levels | Slack |errors
------------------------------------------------------------------------
------------------------------
* TS_dcm_0_dcm_0_CLKFX_BUF = PERIOD TIMEGRP | 10.160ns | 220.189ns |
0 | -210.029ns | 173
"dcm_0_dcm_0_CLKFX_BUF" TS_sys_c | | |
| |
lk_pin / 1.47619048 HIGH 50% | | |
| |
------------------------------------------------------------------------
------------------------------
* TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 14.999ns | 119.031ns |
2 | -104.032ns | 244
"dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin | | |
| |
HIGH 50% | | |
| |
------------------------------------------------------------------------
------------------------------
* TS_dcm_1_dcm_1_CLK90_BUF = PERIOD TIMEGRP | 10.160ns | 74.095ns |
0 | -63.935ns | 4
"dcm_1_dcm_1_CLK90_BUF" TS_dcm_0 | | |
| |
_dcm_0_CLKFX_BUF PHASE 2.54 ns HIGH 50% | | |
| |
------------------------------------------------------------------------
------------------------------
* NET "fpga_0_Ethernet_MAC_PHY_rx_clk_ibuf" | 2.000ns | 2.968ns |
0 | -0.968ns | 1
MAXSKEW = 2 ns | | |
| |
------------------------------------------------------------------------
------------------------------
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_ibuf" | 2.000ns | 1.580ns |
0 | 0.420ns | 0
MAXSKEW = 2 ns | | |
| |
------------------------------------------------------------------------
------------------------------
TS_dcm_2_dcm_2_CLK90_BUF = PERIOD TIMEGRP | 10.000ns | 9.359ns |
0 | 0.641ns | 0
"dcm_2_dcm_2_CLK90_BUF" TS_fpga_ | | |
| |
0_DDR_CLK_FB PHASE 2.5 ns HIGH 50% | | |
| |
------------------------------------------------------------------------
------------------------------
TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | 6.000ns | 4.983ns |
1 | 1.017ns | 0
RP "PADS" TO TIMEGRP "RXCLK_GRP_E | | |
| |
thernet_MAC" 6 ns | | |
| |
------------------------------------------------------------------------
------------------------------
TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | 10.000ns | 2.912ns |
0 | 7.088ns | 0
GRP "TXCLK_GRP_Ethernet_MAC" TO T | | |
| |
IMEGRP "PADS" 10 ns | | |
| |
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