Doug,
I am also having issues with
meeting timing with the reference
design an EDK 9.1.02. I’ve tried numerous things but haven’t quite
gotten there. Here’s a summary of what I’ve done (with some
success).
Put the “–timing;” in the map
section of
./etc/fast_runtime.opt. (as Jim Van Vorst suggested)
Add IOBDELAY=NONE to your
./data/system.ucf file on your *DDR_DQ_pin*
and *DDR_DQS_pin* pins.
I also added input buffers to
the ethernet tx_clk and rx_clk inputs
to insure IBUFGs were available for the other clock pins. This is what
Avnet
did for their uClinux reference design. This is trickier and requires
a folder/files
to be added in your pcores directory.
I’m running the reference design
back through the tools with
all the above modifications and should be able to report shortly if it
worked.
Jim
Hello,
I am trying to
build the Petalinux
Xilinx-Spartan3E1600-RevA-edk91 reference design using Platform Studio
Release
Version: 9.1.02i, Application Version: Build EDK_J_SP2.4+0. The PAR
output from
bitstream generation says that the design did not meet timing and lists
constraints that have not been met (the output is listed below). I am
wondering
what I am doing wrong. The bitstream works on one of my 1600E
evaluation boards
but fails intermittently on another (while u-boot is running). I am new
to XPS
and microblaze so any advice is greatly appreciated.
Thank you,
Doug
Generating "PAR"
statistics.
**************************
Generating Clock
Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock
Net | Resource |Locked|Fanout|Net
Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|
DBG_CLK_s | BUFGMUX_X1Y11| No | 154 |
0.243 | 0.548 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_Ethernet_MAC_
|
| |
|
| |
|PHY_rx_clk_pin_BUFGP
|
| |
|
| |
|
| BUFGMUX_X1Y10| No | 19 |
0.032 | 0.549 |
+---------------------+--------------+------+------+------------+-------------+
|
ddr_dev_clk_s
| BUFGMUX_X2Y11| No | 140 |
0.178 | 0.551 |
+---------------------+--------------+------+------+------------+-------------+
|
ddr_clk_90_s | BUFGMUX_X1Y1| No | 76 |
0.200 | 0.542 |
+---------------------+--------------+------+------+------------+-------------+
|
ddr_dev_clk_90_s |
BUFGMUX_X0Y3| No | 16 |
0.014 | 0.232 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_Ethernet_MAC_
|
| |
|
| |
|PHY_tx_clk_pin_BUFGP
|
| |
|
| |
|
|
BUFGMUX_X1Y0| No | 32 |
0.119 | 0.543 |
+---------------------+--------------+------+------+------------+-------------+
|
dlmb_port_BRAM_Clk | BUFGMUX_X2Y10|
No | 4333 | 0.292 |
0.552 |
+---------------------+--------------+------+------+------------+-------------+
|ethernet_mac/etherne
|
| |
|
| |
|t_mac/SG_DMA.XEMAC_I
|
| |
|
| |
|/inst_EMAC/rState<35
|
| |
|
| |
|
> | Local|
| 11 | 0.000 |
1.370 |
+---------------------+--------------+------+------+------------+-------------+
|opb_intc_0/opb_intc_
|
|
|
|
| |
|0/INTC_CORE_I/MANY_I
|
| |
|
| |
|NTR_DET_GEN.INTR_DET
|
| |
|
| |
|
_I/interrupts<4>
|
Local| | 1 |
0.000 | 1.180 |
+---------------------+--------------+------+------+------------+-------------+
|opb_intc_0/opb_intc_
|
| |
|
| |
|0/INTC_CORE_I/MANY_I
|
| |
|
| |
|NTR_DET_GEN.INTR_DET
|
| |
|
| |
|
_I/interrupts<2>
|
Local| | 1 |
0.000 | 1.193 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_DDR_CLK_FB_IB
|
| |
|
| |
|
UFG |
Local| | 4 |
0.000 | 3.077 |
+---------------------+--------------+------+------+------------+-------------+
|debug_module/bscan_u
|
| |
|
| |
|
pdate |
Local| | 1 |
0.000 | 0.830 |
+---------------------+--------------+------+------+------------+-------------+
|
sys_clk_pin_IBUFG
|
Local| | 4 |
0.372 | 2.372 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the
difference between the minimum and
maximum routing
only delays for
the net. Note this is different from
Clock Skew which
is reported in
TRCE timing report. Clock Skew is the
difference between
the minimum and
maximum path delays which includes
logic delays.
Timing Score:
625412
WARNING:Par:62 -
Your design did not meet
timing. The following are some suggestions to assist you to meet
timing in
your design.
Review the
timing
report using Timing Analyzer (In ISE select "Post-Place &
Route
Static Timing
Report"). Go to the failing constraint(s) and select
the "Timing
Improvement Wizard" link for suggestions to correct each problem.
Rerun Map with
"-timing" (ISE
process "Perform Timing -Driven
Packing and
Placement"
Run Multi-Pass
Place and Route in PAR
using at least 5 "PAR Iterations"
(ISE process
"Multi Pass Place
& Route").
Use the Xilinx
"xplorer" script
to try special combinations of
options known
to produce very good
results.
See
http://www.xilinx.com/ise/implementation/Xplorer.htm for details.
Visit the
Xilinx technical support web
at http://support.xilinx.com and go to
either
"Troubleshoot->Tech
Tips->Timing & Constraints" or "
TechXclusives->Timing Closure"
for tips and suggestions for meeting timing
in your design.
INFO:Timing:3284
- This timing report was generated
using estimated delay
information.
For accurate numbers,
please refer to the post Place and Route
timing report.
Asterisk (*)
preceding a constraint indicates it was
not met.
This may be
due to a setup or hold
violation.
------------------------------------------------------------------------------------------------------
Constraint
| Check | Worst Case | Best Case | Timing |
Timing
| |
Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
*
TS_dcm_0_dcm_0_CLKFX_BUF = PERIOD TIMEGRP |
SETUP | -4.053ns|
174.912ns| 189| 500180
"dcm_0_dcm_0_CLKFX_BUF"
TS_sys_c | HOLD |
0.927ns|
|
0| 0
lk_pin /
1.47619048 HIGH
50%
|
|
|
|
|
------------------------------------------------------------------------------------------------------
*
TS_dcm_1_dcm_1_CLK90_BUF = PERIOD TIMEGRP |
SETUP | -2.704ns|
86.051ns|
8| 18590
"dcm_1_dcm_1_CLK90_BUF"
TS_dcm_0 | HOLD |
1.670ns|
|
0| 0
_dcm_0_CLKFX_BUF PHASE 2.54 ns HIGH
50% |
|
|
|
|
------------------------------------------------------------------------------------------------------
*
TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP |
SETUP | -2.514ns|
92.907ns| 128| 39167
"dcm_0_dcm_0_CLK0_BUF"
TS_sys_clk_pin | HOLD
|
0.717ns|
| 0|
0
HIGH
50%
|
|
|
|
|
------------------------------------------------------------------------------------------------------
*
TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG |
MAXDELAY| -1.849ns|
7.849ns| 37|
67475
RP "PADS" TO
TIMEGRP "RXCLK_GRP_E
|
|
|
|
|
thernet_MAC" 6
ns
| |
|
|
|
------------------------------------------------------------------------------------------------------
NET
"fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW |
0.323ns| 1.677ns|
0| 0
UFGP" MAXSKEW =
2
ns
|
|
|
| |
------------------------------------------------------------------------------------------------------
NET
"fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW |
1.890ns| 0.110ns|
0| 0
UFGP" MAXSKEW =
2
ns
|
|
|
|
|
------------------------------------------------------------------------------------------------------
NET
"fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP
| 6.248ns|
22.148ns|
0| 0
UFGP" PERIOD =
40 ns HIGH 14
ns |
HOLD |
1.143ns|
| 0|
0
------------------------------------------------------------------------------------------------------
TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME |
MAXDELAY| 7.088ns|
2.912ns|
0| 0
GRP
"TXCLK_GRP_Ethernet_MAC"
TO T
|
|
|
| |
IMEGRP "PADS"
10
ns
|
|
|
|
|
------------------------------------------------------------------------------------------------------
TS_sys_clk_pin
= PERIOD TIMEGRP
"sys_clk_ | SETUP |
12.789ns| 2.210ns|
0| 0
pin" 14.999 ns
HIGH
50%
| HOLD |
0.453ns|
|
0| 0
------------------------------------------------------------------------------------------------------
NET
"fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP
| 19.052ns|
10.689ns|
0| 0
UFGP" PERIOD =
40 ns HIGH 14
ns |
HOLD |
0.949ns|
|
0| 0
------------------------------------------------------------------------------------------------------
4 constraints not
met.
Generating Pad
Report.
All signals are
completely routed.
Total REAL time
to PAR completion: 13 mins 20 secs
Total CPU time to
PAR completion: 10 mins 50 secs
Peak Memory
Usage: 418 MB
Placement:
Completed - No errors found.
Routing:
Completed - No errors found.
Timing: Completed
- 362 errors found.
Number of error
messages: 0
Number of warning
messages: 7
Number of info
messages: 0
Writing design to
file system.ncd
PAR done!