[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[microblaze-uclinux] RE: PVR support for FDT
There is apparently an issue here, which is fixed in v7.10b
"When using MicroBlaze version 7.00b, turning on the MMU causes the PVR
values to be messed up. A work-around is to set C_MMU_TLB_ACCESS to 0 or
2."
Steve
> -----Original Message-----
> From: Michal Simek [mailto:Monstr@xxxxxxxxx]
> Sent: Tuesday, April 08, 2008 8:40 AM
> To: Stephen Neuendorffer
> Subject: PVR support for FDT
>
> Hi Steve,
>
> I found one bad behavior with PVR. This is my CPU description in MHS
and output from XMD. You can see
> MHS description coresponds with text description in xmd. But
description in PVR reg is weird. There
> are no USER regs, no settings for MUL, DIV, SHIFT and others.
> I tried the same issue on different design(same board, MB 7.00.a and
b) but the results are the same.
>
> Don't you know anything about?
>
> Thanks,
> Michal
>
>
>
>
> BEGIN microblaze
> PARAMETER HW_VER = 7.00.b
> PARAMETER INSTANCE = microblaze_0
> PARAMETER C_USE_FPU = 2
> PARAMETER C_USE_ICACHE = 1
> PARAMETER C_USE_DCACHE = 1
> PARAMETER C_DEBUG_ENABLED = 1
> PARAMETER C_ICACHE_BASEADDR = 0x20000000
> PARAMETER C_ICACHE_HIGHADDR = 0x21ffffff
> PARAMETER C_DCACHE_BASEADDR = 0x20000000
> PARAMETER C_DCACHE_HIGHADDR = 0x21ffffff
> PARAMETER C_USE_BARREL = 1
> PARAMETER C_USE_HW_MUL = 2
> PARAMETER C_USE_DIV = 1
> PARAMETER C_FPU_EXCEPTION = 1
> PARAMETER C_DIV_ZERO_EXCEPTION = 1
> PARAMETER C_DPLB_BUS_EXCEPTION = 1
> PARAMETER C_IPLB_BUS_EXCEPTION = 1
> PARAMETER C_ILL_OPCODE_EXCEPTION = 1
> PARAMETER C_OPCODE_0x0_ILLEGAL = 1
> PARAMETER C_UNALIGNED_EXCEPTIONS = 1
> PARAMETER C_USE_MMU = 3
> PARAMETER C_MMU_ZONES = 2
> PARAMETER C_NUMBER_OF_PC_BRK = 2
> PARAMETER C_FAMILY = spartan3e
> PARAMETER C_INSTANCE = microblaze_0
> PARAMETER C_FSL_LINKS = 1
> PARAMETER C_CACHE_BYTE_SIZE = 16384
> PARAMETER C_DCACHE_BYTE_SIZE = 16384
> PARAMETER C_PVR = 2
> PARAMETER C_PVR_USER1 = 0x12
> PARAMETER C_PVR_USER2 = 0x12345678
> BUS_INTERFACE DPLB = mb_plb
> BUS_INTERFACE IPLB = mb_plb
> BUS_INTERFACE ixcl = ixcl
> BUS_INTERFACE dxcl = dxcl
> BUS_INTERFACE DEBUG = microblaze_0_dbg
> BUS_INTERFACE SFSL0 = download_link
> BUS_INTERFACE DLMB = dlmb
> BUS_INTERFACE ILMB = ilmb
> PORT RESET = mb_reset
> PORT Interrupt = Interrupt
> END
>
> MicroBlaze Processor Configuration :
> -------------------------------------
> Version............................7.00.b
> Optimization.......................Performance
> Interconnect.......................PLBv46
> MMU Type...........................Full_MMU
> No of PC Breakpoints...............2
> No of Read Addr/Data Watchpoints...0
> No of Write Addr/Data Watchpoints..0
> Instruction Cache Support..........on
> Instruction Cache Base Address.....0x20000000
> Instruction Cache High Address.....0x21ffffff
> Data Cache Support.................on
> Data Cache Base Address............0x20000000
> Data Cache High Address............0x21ffffff
> Exceptions Support................on
> FPU Support.......................on
> Hard Divider Support...............on
> Hard Multiplier Support............on - (Mul64)
> Barrel Shifter Support.............on
> MSR clr/set Instruction Support....on
> Compare Instruction Support........on
> Number of FSL ports................1
> PVR Supported......................on
> PVR Configuration Type.............Full
>
> Connected to MDM UART Target
> Connected to "mb" target. id = 0
> Starting GDB server for "mb" target (id = 0) at TCP port no 1234
> XMD% srrd
> pc: 21a06880 msr: 000004a2 ear: 00000000 esr: 00000000
> fsr: 00000000 btr: 00000000 pvr0: 80000012 pvr1: 00000038
> pvr2: 00000033 pvr3: 80000000 pvr4: 80000000 pvr5: 80000000
> pvr6: 00000000 pvr7: 0000003f pvr8: 00000000 pvr9: 0000003f
> pvr10: 00000000 pvr11: 80000000
> XMD%
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/