Re: [microblaze-uclinux] quickly check vhdl syntax

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

Hi Sebsatian, Graeme,

Graeme Smecher wrote:

> Sebastian wrote:

> > i added my own ip in xps to a system for running petalinux. is there 
> > any possibility to check the vhdl syntax of my user_logic.vhd before 
> > executing 'make -f system.make bits' because with this command it 
> > takes about 20 minutes to get a report if there is any syntax error in 
> > my source code.
> > i tried to use 'ghdl -s user_logic.vhd' but with it i always get the 
> > error:

>   * move your IP closer to the top of your hardware description file 
> (system.mhs), since they are processed in order. Or,
>   * create a stripped-down 'xst' project by hand and use it to do your 
> syntax checking.

There is a third, even easier way.

After you've done a "make netlist" run in your EDK project, you can just

$ cd synthesis
$ xst -ifn my_ip_wrapper_xst.scr

to launch XST on your component.

Rinse and repeat until clean building happiness is yours!

If you change any params then you'll need to rerun the make netlist 
phase, but it's usually pretty quick.  You can actually ^C this after 
it's finished generating the VHDL and project files, no need to wait for 
it to run XST on everything.

Regards,

John

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