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Re: [microblaze-uclinux] OPB ETERNET LITE ISSUE
By analyzing the timing report it seems that the DDR feedback is failing
to propagate within the given constraints.
================================================================================
Timing constraint: OFFSET = IN -0.75 ns VALID 3.5 ns BEFORE COMP
"fpga_0_DDR_CLK_FB" TIMEGRP DDR_FEEDBACK_CLOCK_PHASE_90;
18 items analyzed, 18 timing errors detected. (0 setup errors, 18 hold
errors)
Offset is -5.628ns.
--------------------------------------------------------------------------------
Hold Paths: OFFSET = IN -0.75 ns VALID 3.5 ns BEFORE COMP
"fpga_0_DDR_CLK_FB" TIMEGRP
DDR_FEEDBACK_CLOCK_PHASE_90;
--------------------------------------------------------------------------------
Slack (hold path): -4.268ns (requirement - (clock path + clock
arrival + uncertainty - data path))
Source: fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> (PAD)
Destination:
DDR_SDRAM_32Mx16/DDR_SDRAM_32Mx16/DDR_CTRL_I/WO_ECC.IO_REG_I/NOT_VIRTEX4_IOREGS.INPUT_DDR_REGS_GEN[7].RDDATA_HIREG (FF)
Destination Clock: ddr_clk_90_s rising at 2.500ns
Requirement: 4.250ns
Data Path Delay: 0.956ns (Levels of Logic = 0)
Clock Path Delay: 6.974ns (Levels of Logic = 3)
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Data Path: fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> to
DDR_SDRAM_32Mx16/DDR_SDRAM_32Mx16/DDR_CTRL_I/WO_ECC.IO_REG_I/NOT_VIRTEX4_IOREGS.INPUT_DDR_REGS_GEN[7].RDDATA_HIREG
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tioickp (-Th) -0.956 fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7>
iobuf_17/IBUF
DDR_SDRAM_32Mx16/DDR_SDRAM_32Mx16/DDR_CTRL_I/WO_ECC.IO_REG_I/NOT_VIRTEX4_IOREGS.INPUT_DDR_REGS_GEN[7].RDDATA_HIREG
---------------------------- ---------------------------
Total 0.956ns (0.956ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
Clock Path: fpga_0_DDR_CLK_FB to
DDR_SDRAM_32Mx16/DDR_SDRAM_32Mx16/DDR_CTRL_I/WO_ECC.IO_REG_I/NOT_VIRTEX4_IOREGS.INPUT_DDR_REGS_GEN[7].RDDATA_HIREG
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.726 fpga_0_DDR_CLK_FB
fpga_0_DDR_CLK_FB_IBUFG
net (fanout=4) 5.485 fpga_0_DDR_CLK_FB_IBUFG
Tdcmino -2.538 dcm_2/dcm_2/Using_Virtex.DCM_INST
net (fanout=1) 0.462 dcm_2/dcm_2/CLK90_BUF
Tgi0o 1.457
dcm_2/dcm_2/Using_BUGF_for_CLK90.CLK90_BUFG_INST
net (fanout=80) 0.382 ddr_clk_90_s
---------------------------- ---------------------------
Total 6.974ns (0.645ns logic, 6.329ns route)
--------------------------------------------------------------------------------
...
(I'm not posting the whole report)
...
Below the relevant UCF line:
OFFSET = IN -0.750 ns VALID 3.5 ns BEFORE fpga_0_DDR_CLK_FB TIMEGRP
DDR_FEEDBACK_CLOCK_PHASE_90 ;
The same applies for the other constraint
(DDR_FEEDBACK_CLOCK_PHASE_270).
I just managed to lighten the project and the routing got scrambled.
Is there anything that could easily be done in such cases?
I'm quite new to this sort of things, so please excuse my ignorance.
Many thanks.
PS: sorry for the subject in bold (didn't want to be showy).
> Hello everybody,
>
> sorry to bother you, but I'm stuck on a problem I could not overcome
> with my limited knowledge.
>
> I'm facing a very similar problem to what has been reported by Douglas
> Bruey in
> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/archive/2007/10/msg00029.html
>
> I'm using a Spartan3E1600E Microblaze edition board with a
> xc3s1600e-gf320-4 on top of it. I just wanted to switch from the full
> Ethernet core to the lite version.
>
> I started by editing the petalinux release
> Xilinx-Spartan3E1600-RevA-edk91 (it seems to me that the 9.2 release is
> targetted to some other evaluation board)
>
> - Commented in UCF the lines regarding PHY_Mii_clk and PHY_Mii_data
> since these are not implemented in ethernet lite interface
> - Copied ethernetlite section from system.mhs used in
> Xilinx-Spartan3E500-RevD-edk91 with some minor adjustements (opb clock
> to 66MHz and address)
> - Changed emac to emaclite in system.mss
> - Generated new bitstream
>
> In the software project I accordingly changed the network driver to
> support emaclite instead of emac.
>
> These are the relevant sections relevant to the EMAC core in EDK:
>
> -- system.ucf --
>
> Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=T7;
> Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=V3;
> Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=U13;
> Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=V2;
> Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=V8;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=T11;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=U11;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=V14;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=U6;
> Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U14;
> Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=P16;
> Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=R11;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=T15;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=R5;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=T5;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVCMOS33;
>
>
> -- system.mhs --
>
> PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin =
> fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I, BUFFER_TYPE = IBUF
> PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin =
> fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I, BUFFER_TYPE = IBUF
> PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR
> = I
> PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR =
> I
> PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin =
> fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
> PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR
> = I
> PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er,
> DIR = I
> PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en,
> DIR = O
> PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin =
> fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
>
>
> BEGIN opb_ethernetlite
> PARAMETER INSTANCE = Ethernet_MAC
> PARAMETER HW_VER = 1.01.b
> PARAMETER C_OPB_CLK_PERIOD_PS = 15000
> PARAMETER C_BASEADDR = 0x40c00000
> PARAMETER C_HIGHADDR = 0x40c0ffff
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk = sys_clk_s
> PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
> PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
> PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
> PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
> PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
> PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
> PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
> PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
> PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
> PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
> END
>
>
> -- system.mss --
>
> BEGIN DRIVER
> PARAMETER DRIVER_NAME = emaclite
> PARAMETER DRIVER_VER = 1.11.a
> PARAMETER HW_INSTANCE = Ethernet_MAC
> END
>
> Having read what Douglas wrote I double checked the presence of the opb
> clock line.
>
> I'm experiencing a hang between the fs-boot and u-boot boot process.
>
> =================================================
> FS-BOOT First Stage Bootloader (c) 2006 PetaLogix
> =================================================
> FS-BOOT: System initialisation completed.
> FS-BOOT: Booting from FLASH. Press 's' for image download.
> FS-BOOT: Waiting for SREC image....
> FS-BOOT: Image download successful.
> FS-BOOT: Warning image location differ from default boot location. Image
> will not boot automatically after POR.
> FS-BOOT: Press 'n' to boot old image.
> FS-BOOT: Use new image.
> FS-BOOT: Booting image...
>
> If i stop the fs-boot with the 's' key and debug with xmd i see that
> main memory (DDR) is not working correctly: if i write to 0x47FC0000
> (RAM address space is 0x44000000-0x47FFFFFF) i always read back 1024.
>
> Now the question is: why memory cannot be read back?
>
> If I reload the original project I can normally boot.
>
> The only thing I've done is to substitute OPB Ethernet with OPB Ethernet
> Lite.
>
> I would be very grateful if somebody could point me in the right
> direction to better understand my problem or give me some hints on how
> (and what) to debug.
>
> Watching the fpga editor seems there is huge difference between the two
> cores. Hope it is not a routing issue.
>
> Many thanks for your time and consideration.
>
> Giulio Mazzoleni
>
> ___________________________
> microblaze-uclinux mailing list
> microblaze-uclinux@xxxxxxxxxxxxxx
> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>
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