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[microblaze-uclinux] simulate my design
- To: microblaze-uclinux@xxxxxxxxxxxxxx
- Subject: [microblaze-uclinux] simulate my design
- From: Sebastian <fatfpga@xxxxxxxxxxxxxx>
- Date: Wed, 07 May 2008 12:25:10 +0200
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hi!
i've got a strange problem with my user logic. but to debug this, i cannot use try-and-error every time
because it takes so much time to compile and synthesize the whole design.
so i got the idea to simulate my design - but i don't know if this is possible.
can i simulate only my ip logic or also simulate the complete system? i cannot imagine how that would work.
would anybody be so kind and help me with some hints or document-links how to achieve this?
i'm using xilinx edk and ise 9.1.
thank you in advance
sebastian
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