Re: [microblaze-uclinux] simulate my design

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

Hi Sebstien,

Sebastian wrote:

> i've got a strange problem with my user logic. but to debug this, i 
> cannot use try-and-error every time
> because it takes so much time to compile and synthesize the whole design.
> so i got the idea to simulate my design - but i don't know if this is 
> possible.
> can i simulate only my ip logic or also simulate the complete system? i 
> cannot imagine how that would work.
> would anybody be so kind and help me with some hints or document-links 
> how to achieve this?
> i'm using xilinx edk and ise 9.1.

You have a few options - you can use the BFM (Bus Functional Model) 
toolkit from IBM, with Xilinx tools and Model Sim, to simulate just the 
interesting bits of your design.

e.g. for a PLB device, you would just instantiate a bus and your IP, 
then write a little BFM script that initiates transactions on the bus.

Just search xilinx.com for BFM, you'll find some appnotes etc.

The ISE simulator is ... functional, although I've seen it do some 
pretty wierd things in my tests with it.

I'm not sure if you can use BFM with ISE simulator - has anybody tried?

If you can't you have to roll your own testbenches.  You'll want to 
create minimal test systems rather than the entire CPU and peripheral 
subsystems.

That's fine if it's using FSL or something simple like that, but 
creating your own PLB driver in simulation just to test your core is a 
pain (which is what's so nice about BFM).

If you have external interfaces to worry about, or memories, then it 
just keeps getting more complex still...

There's a reason why verification can be 70-90% of total costs for 
serious chip designers!

Cheers,

John


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