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RE: [microblaze-uclinux] MMU version throwing illegal instruction exception
You should use the latest version possible, preferably some version of
7.10, at least 7.00.b *with* the AR patch below. You are bound to have
problems with interrupts on 7.00.a.
AR #30051 - 9.2i EDK - MicroBlaze v7.00.b tactical patch
AR #30276 - 10.1 EDK - MicroBlaze v7.00.b tactical patch
AR #29784 - 9.2i EDK - In MicroBlaze v7.00.a, erroneous exceptions
following an interrupt can occur
Steve
> -----Original Message-----
> From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On
> Behalf Of william.orfitelli@xxxxxxxxx
> Sent: Thursday, May 08, 2008 3:01 PM
> To: john.williams@xxxxxxxxxxxxx; monstr@xxxxxxxxx
> Cc: microblaze-uclinux@xxxxxxxxxxxxxx
> Subject: [microblaze-uclinux] MMU version throwing illegal instruction
exception
>
>
> John, Mike, and the reflector....
>
> Our MMU based kernel has a few issues... here is one that has us
pulling hair!
> Thanks for any insights...
>
>
> The symptom:
>
> When logging in, or simply typing 'ls' an exception is randomly
thrown:
>
>
> ~ # ls
> Oops: Exception in kernel mode, sig: 4
> Registers dump: mode=1
> sp=C0219E44, r2=00000000, r3=00000001, r4=00000000
> r5=C0340990, r6=C0340994, r7=00000353, r8=00000001
> r9=00000001, r10=00000000, r11=000044AA, r12=C0007608
> r13=00000000, r14=C02B4000, r15=C00280D4, r16=C006CA98
> r17=C0058F00, r18=00000000, r19=C0058B9C, r20=C03EA020
> r21=C0040454, r22=C0218000, r23=C0882F24, r24=C0882F24
> r25=00014800, r26=C006CA78, r27=C08466E4, r28=C004ACD8
> r29=00000004, r30=C0059020, r31=C02F92AC, rPC=C0168AEC
> ear=00014800, esr=C0845C88
> Illegal instruction
>
> The kernel recovers almost all of the time from this. Almost being
the operative word.
>
> Note that the rPC of C0168AEC is a zeroed out area after _etext. which
is c0168ad8.
>
> We think that when in __down_read, at the very end, when interrupts
are enabled, an interrupt occurs
> that then causes an MMU exception. On return from the interrupt,
execution starts after the correct
> address for the instruction. This is just a guess...
>
> I have not been able to catch this in the page fault routine.
> To catch this I put a hardware breakpoint at
"illegal_opcode_trap_wrapper:" The debugger register
> output is below.
>
>
>
>
>
> Configuration:
>
> We are using the PetaLogix MMU distro mmu-v0.10.
> Ours is a custom board, with a Virtex5.
> We have 512M of DRAM, and are using the UartLite.
> I tried to match the config settings from the ML505 example.
>
>
>
>
> From GDB:
>
> MicroBlaze Processor Configuration :
> -------------------------------------
> Version............................7.00.a
> Optimization.......................Performance
> Interconnect.......................PLBv46
> MMU Type...........................Full_MMU
> No of PC Breakpoints...............1
> No of Read Addr/Data Watchpoints...0
> No of Write Addr/Data Watchpoints..0
> Instruction Cache Support..........on
> Instruction Cache Base Address.....0x80000000
> Instruction Cache High Address.....0x9fffffff
> Data Cache Support.................on
> Data Cache Base Address............0x80000000
> Data Cache High Address............0x9fffffff
> Exceptions Support................on
> FPU Support.......................off
> Hard Divider Support...............on
> Hard Multiplier Support............on - (Mul64)
> Barrel Shifter Support.............on
> MSR clr/set Instruction Support....on
> Compare Instruction Support........on
> PVR Supported......................on
> PVR Configuration Type.............Full
>
> Thanks again,
>
> Bill Orfitelli
>
>
>
>
> Eastman Kodak Company
> Phone: (585) 588-7219
> Email: william.orfitelli@xxxxxxxxx
<mailto:william.orfitelli@xxxxxxxxx>
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