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Re: [microblaze-uclinux] Help with ddr sdram



Well this is not easy and there is more  complication to it when the controller is in the field, extrea delays might be introduced like from  heat .. Etc. The best practice is to use a controllable delay feedback circuit you can use an FSM to do it and by edge detection you can always assume your best delay, the Dqs will be your best candidate as you know how it is going to hit and then usually you have frequent 0 to one or one to zero transition from which you can predict your delay , you have to keep track always for the estimated delay so that your controller won't fail because of any extrnal parameters

On 27 May 2007, at 19:45, "Ibrahim Magdy" <bibo1978@xxxxxxxxx> wrote:

I am not sure I get you right, but simply if you don't have a Feedback clock for DDr in your board you can remove external pad use a DCM with a secific delay related to your track delay.

On 5/24/07, pantgom@xxxxxxx <pantgom@xxxxxxx> wrote:
Hi everyone, I want to design a model with uClinux in my Smt338. This is a
Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16 as
DDR memory. First of all I need to implement the hardware architecture, so
I use edk 8.1 (or edk 8.2) to create a model with PowerPC and this DDR
memory. In the ucf I map every port, but I have not any pin to DDR_CLK,
that is, the feedback ddr clock.

This is the loc entry: Net fpga_0_GEN_DDR_CLK_FB LOC=;

What can I do?. Perhaps I could use a DCM_module but I don't know how
could I implement it.

Regards


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Bibo1978,

  Everything should be made as simple as possible, but not simpler