Sebastian wrote:
1.
i created an embedded system based on the petalinux reference design for
spartan-3e1600 and edk 9.1.
i added my own ip which creates some data that is written to a included
ipif-readfifo.
i use the ipif-dma s/g controller to transfer the data to the system ddr
ram. i've written a testing
program to benchmark the transfer rate. my results are about 16 MByte /
s. i've estimated a transfer
rate about 200 mbyte / s if the dma-c uses burst mode an no one else is
using the opb.
could it be that the ddr sdram is the bottleneck? i read something about
ddr ram burst mode an i think
this isn't enabled in the reference design. can anyone help me out with
some information?
The mch_opb_ddr controller has a parameter C_INCLUDE_OPB_BURST_SUPPORT,
which defaults to zero. You might like to enable that and retest your
performance.
Similarly if you upgrade to newer tools and the MPMC, it has
C_SPLB*_SUPPORT_BURSTS parameters for burst support on PLB PIMs.
2.
in my own ip, i'm filling the fifo with data. once it is full, i want to
initialize a dma transfer.
so i have to trigger that transfer from within my userlogic.vhd with
writing into the LENGTH register
of the dma controller. how can i achieve this? i cannot write into the
dma s/g registers, can i?
Are you using the S/G DMA functionality of the IPIF, or is it a
sstandalone DMA controller? If it's the first one, then there's an IPIF
signal protocol for setting DMA transaction parameters, I believe.
Check the IPIF documentation.
If you have a standalone DMA controller then the transaction will need
to be configured into it's OPB/PLB registers somehow, either by a SW
dirver or your core bus mastering to write the params. Not very
efficient.
3.
to see how the dma-c transfers the data over the bus, it would be very
useful to see all the bussignals.
i read something about the bus functional model testing but i think i
need some extra software for this:
chipscope or modelsim? can i simulate without buying this extra
software?
You can use the BFM toolkit and modelsim. ModelSim XE is free but only
works on Windows.
Or, ChipScope can watch signals live on the FPGA.
Otherwise, maybe route the bus signals to external pins and hook up a
logic analyser.