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I have applied the patches allowing me to use the ll_temac
driver in petalinux but I am still having problems getting the temac to work
properly. The kernel/drivers build fine, the OS boots and the temac
initialises ok. However, I cannot ping anything on my network. On further investigation I have found that the Xilinx_dma_tx_int
irq does get incremented when attempting to ping but the Xilinx_dma_rx_int irq does
not change when pinging to the board – or ever! The driver is able to interface with the PHY properly as it
reports PHY carrier lost/restored when disconnecting the ethernet lead. I have confirmed that the IRQs used by linux match those
used in EDK. I know that this driver is still in development but would
really appreciate it if someone could let me know if they have any ideas. Board/Build Info Spartan 3A dsp 1800 EDK (10.1.2 SP2) ISE IP update 2 Petalinux-v0.30-rc1 lltemac patch posted on 27 May 08 Boot output (debug turned on) : Nb. I have cut out anything not relating to the temac and
cut a few sections which are repeated values. ----------------------------------------------------------------------- XLlTemac_CfgInitialize XLlTemac_Reset resetting the receiver resetting the transmitter waiting until reset is done XLlTemac InitHw XLlTemac InitHw XLlTemac InitHw: disabling receiver XLlTemac_SetOptions current control regs: RCW1: 0x6800ffee; TC: 0x5a000000 Options: 0x278; default options: 0x3f8 setOptions: enabling fcs stripping setOptions: enabling fcs insertion setOptions: writting rcw1: 0x4800ffee setOptions: endabling flow control setOptions: rcw1 is now (fcc): 0x4800ffee setOptions: rcw1 is now (afm): 0x4800ffee setOptions: rcw1 is now (raf): 0x4800ffee setOptions: rcw1 is now (raf2): 0x4800ffee setOptions: rcw1 is now (end): 0x4800ffee setOptions: returning SUCCESS Xtemac_ClearOptions: 0xfffffc07 Xtemac_ClearOptions: disabling jumbo Xtemac_ClearOptions: disabling vlan Xtemac_ClearOptions: setting TC: 0x12000000 Xtemac_ClearOptions: setting RCW1: 0xffee Xtemac_ClearOptions: disabling promiscuous mode Xtemac_ClearOptions: setting AFM: 0x0 XLlTemac_PhySetMdioDivisor XLlTemac InitHw: done Temac_CfgInitialize: returning SUCCESS XLlTemac_SetMacAddress: setting mac address to:
0x00000000 a
35 5
5 8 xilinx_lltemac xilinx_lltemac.0: MAC address is now 0:
a:35: 5: 5: 8 xilinx_lltemac xilinx_lltemac.0: XLlTemac: using DMA mode. XLlTemac: Dma base address: phy: 0x84600180, virt:
0x84600180 XLlTemac: buffer descriptor size: 32768 (0x8000) XLlTemac: Allocating DMA descriptors with
kmalloc<6>XLlTemac: (buffer_descriptor _init) phy: 0x883a0000, virt: 0x883a0000, size: 0x8000 XLlTemac_PhyRead: BaseAddress: 0x81c00000 XLlTemac_PhyRead: Mii Reg: 0x1; Value written: 0x3e1 . . . XLlTemac_PhyRead: Mii Reg: 0x1; Value written: 0x21 XLlTemac_PhyRead: Value retrieved: 0x7969 XTemac: PHY detected at address 1. xilinx_lltemac xilinx_lltemac.0: eth0: Xilinx TEMAC at
0x81C00000 mapped to 0x81 C00000, irq=6 . . . Setting up interface eth0: XLlTemac_SetMacAddress: setting mac address to:
0x00000000 a
35 5
5 8 XLlTemac_SetOptions current control regs: RCW1: 0xffee; TC: 0x12000000 Options: 0x3fa; default options: 0x3f8 setOptions: enabling fcs stripping setOptions: enabling fcs insertion setOptions: writting tc: 0x52000000 setOptions: writting rcw1: 0x5000ffee setOptions: endabling flow control setOptions: rcw1 is now (fcc): 0x5000ffee setOptions: rcw1 is now (afm): 0x5000ffee setOptions: rcw1 is now (raf): 0x5000ffee setOptions: rcw1 is now (raf2): 0x5000ffee setOptions: rcw1 is now (end): 0x5000ffee setOptions: returning SUCCESS Xtemac_ClearOptions: 0xfffffc05 Xtemac_ClearOptions: disabling vlan Xtemac_ClearOptions: disabling promiscuous mode Xtemac_ClearOptions: setting AFM: 0x0 eth0: XLlTemac: Options: 0x3fa eth0: XLlTemac: allocating interrupt 0 for dma mode tx. eth0: XLlTemac: allocating interrupt 1 for dma mode rx. XLlTemac_PhyRead: BaseAddress: 0x81c00000 XLlTemac_PhyRead: Mii Reg: 0x1; Value written: 0x21 XLlTemac_PhyRead: Value retrieved: 0x796d XLlTemac_PhyRead: BaseAddress: 0x81c00000 XLlTemac_PhyRead: Mii Reg: 0x1; Value written: 0x21 XLlTemac_PhyRead: Value retrieved: 0x796d XLlTemac_PhyWrite XLlTemac_PhyWrite XLlTemac_PhyWrite XLlTemac_PhyRead: BaseAddress: 0x81c00000 XLlTemac_PhyRead: Mii Reg: 0x1; Value written: 0x21 XLlTemac_PhyRead: Value retrieved: 0x7949 . . . XLlTemac_PhyRead: BaseAddress: 0x81c00000 XLlTemac_PhyRead: Mii Reg: 0x1; Value written: 0x21 XLlTemac_PhyRead: Value retrieved: 0x796d eth0: XLlTemac: We renegotiated the speed to: 1000 XLlTemac_SetOperatingSpeed XLlTemac_SetOperatingSpeed: setting speed to: 1000 (0x3e8) XLlTemac_SetOperatingSpeed: current speed: 0x0 XLlTemac_SetOperatingSpeed: new speed: 0x80000000 XLlTemac_SetOperatingSpeed: done eth0: XLlTemac: speed set to 1000Mb/s XLlTemac_Start enabling transmitter transmitter enabled enabling receiver receiver enabled XLlTemac_Start: done eth0: XLlTemac: Send Threshold = 24, Receive Threshold = 4 eth0: XLlTemac: Send Wait bound = 254, Receive Wait bound =
254 Starting thttpd: XLlTemac_PhyRead: BaseAddress: 0x81c00000 XLlTemac_PhyRead: Mii Reg: 0x0; Value written: 0x20 . . . XLlTemac_PhyRead: Mii Reg: 0x1; Value written: 0x21 XLlTemac_PhyRead: Value retrieved: 0x796d --------------------------------------------------------------------------------------- Cheers Ian. The information contained in this E-Mail and any subsequent
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