RE: [microblaze-uclinux] Memory alignment

["A. Bose" <abose@xxxxxxxx>]

I will do my memory alignment in my modified mpmc core. The MPMC interface
has not changed therefore I believe that the cachelink protocol has not been
affected. This makes sense and I am more familiar in this territory.

Thanks,
A Bose

-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of John Williams
Sent: Thursday, October 02, 2008 7:48 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] Memory alignment

A. Bose wrote:

> I have a modified Xilinx MPMC core that interfaces to SRAM (interface to 
> the XPS remains the same). Each SRAM access is 4x32bit words. So the 
> addressing needs to be 16 byte aligned.
> 
> Where would I change this memory alignment in the kernel?
> 
> Or would there be a better place to do this change?

I'm not sure I understand what you've done.  Attached an SRAM interface 
to MPMC - OK.

But the MicroBlaze interface to MPMC is CacheLink (XCL), which has a 
defined protocol (critical word first, configurable cacheline width).

The kernel won't have anything to do with this, you just need to make 
sure your memory interface can satisfy the cachelink protocol (sparsely 
documented in the MicroBlaze user guide).

Regards,

John

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