Hello, I have thought about that, but if I do not specify the are as cachable would I still be able to access the entire memory segment via the cache. From my understanding there are two ways to the memory controller either via the cache or via the PLB buss and I do not want to go via the PLB buss. BR, Nils -----Original Message----- From: owner-microblaze-uclinux@xxxxxxxxxxxxxx on behalf of Hoefle Marco Sent: Wed 12/3/2008 9:55 AM To: microblaze-uclinux@xxxxxxxxxxxxxx Subject: [microblaze-uclinux] AW: invalidate cache Hello Nils, In your case I would specify the cacheable area in the MHS file of the EDK project. So say for example you have 64 MByte of RAM you could specify the first 60 Mbyte as cacheable and use the remaining 4 MByte for IP data exchange. BR, Marco -----Ursprüngliche Nachricht----- Von: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] Im Auftrag von Nils Hermansson Gesendet: Mittwoch, 3. Dezember 2008 08:50 An: microblaze-uclinux@xxxxxxxxxxxxxx Betreff: invalidate cache Hello, i Wonder if there is any way to invalidate cache for a certain RAM area, I still want to read the ram via the cache since I do not get the speed i need through the PLB buss. Basically what i want todo is to use ioremap and then invalidate the cache for the mapped memory area to be able to read data which external IP blocks has put in the RAM. Best Regards Nils Hermansson ___________________________ microblaze-uclinux mailing list microblaze-uclinux@xxxxxxxxxxxxxx Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
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