[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
AW: [microblaze-uclinux] AW: invalidate cache
Hello Nils,
By default the EDK wizard takes the whole DDR memory address space as cacheable:
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER HW_VER = 7.10.d
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 4096
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 4096
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0x8c000000
PARAMETER C_ICACHE_HIGHADDR = 0x8fffffff
PARAMETER C_DCACHE_BASEADDR = 0x8c000000
PARAMETER C_DCACHE_HIGHADDR = 0x8fffffff
PARAMETER C_AREA_OPTIMIZED = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE ixcl = ixcl
BUS_INTERFACE dxcl = dxcl
BUS_INTERFACE DEBUG = microblaze_0_dbg
PORT MB_RESET = mb_reset
PORT Interrupt = Interrupt
END
In this case the DDR is at 0x8c000000 and the address space is 64Mbyte.
If you change it to:
PARAMETER C_ICACHE_BASEADDR = 0x8c000000
PARAMETER C_ICACHE_HIGHADDR = 0x8f000000
PARAMETER C_DCACHE_BASEADDR = 0x8c000000
PARAMETER C_DCACHE_HIGHADDR = 0x8f000000
then every access between 0x8c000000 and 0x8f000000 will be still fast as it is in the cache range. If you fetch the data from above 0x8f000000 it will be unchached and slower of course. But you should only put the data from/to your external IP in this range. So the linux kernel and the rest of your software should be placed in the cacheable address range so you won't get any performance loss. You can specify in the mss petalogix section which address range is allowed for the kernel.
Hope this helps,
Marco
-----Ursprüngliche Nachricht-----
Von: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] Im Auftrag von Nils Hermansson
Gesendet: Mittwoch, 3. Dezember 2008 10:02
An: microblaze-uclinux@xxxxxxxxxxxxxx
Betreff: RE: [microblaze-uclinux] AW: invalidate cache
Hello,
I have thought about that, but if I do not specify the are as cachable would I still be able to access the entire memory segment via the cache. From my understanding there are two ways to the memory controller either via the cache or via the PLB buss and I do not want to go via the PLB buss.
BR,
Nils
-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx on behalf of Hoefle Marco
Sent: Wed 12/3/2008 9:55 AM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] AW: invalidate cache
Hello Nils,
In your case I would specify the cacheable area in the MHS file of the EDK project. So say for example you have 64 MByte of RAM you could specify the first 60 Mbyte as cacheable and use the remaining 4 MByte for IP data exchange.
BR,
Marco
-----Ursprüngliche Nachricht-----
Von: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] Im Auftrag von Nils Hermansson
Gesendet: Mittwoch, 3. Dezember 2008 08:50
An: microblaze-uclinux@xxxxxxxxxxxxxx
Betreff: invalidate cache
Hello,
i Wonder if there is any way to invalidate cache for a certain RAM area, I still want to read the ram via the cache since I do not get the speed i need through the PLB buss.
Basically what i want todo is to use ioremap and then invalidate the cache for the mapped memory area to be able to read data which external IP blocks has put in the RAM.
Best Regards
Nils Hermansson
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/