RE: [microblaze-uclinux] spi and spidev usage

["Bartsch Carsten" <cbartsch@xxxxxxxxxx>]

Unfortunately I don't remember what the SCLK does when idle. The other lines high is good and I would expect SCLK to do the same. When starting a transmission first SS for one device goes low, later clock and data appear. If SS and data are missing too I would look for the driver. If only clock is missing you might rather look for hardware or FPGA-configuration.

You can test the SPI-core without linux. There is an example in Xilinx-ISE (I used xps_intr_example.c). It is a loopback test but if you remove the loopback option and add a call to XSpi_SetSlaveSelect before Transfer you can see the output.

I'm using an old SPI-core (1.11a). I don't know if there is a driver-problem with the new one or if the behavior is different.

 

I hope you get this running,

Carsten

 

De: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] En nombre de Matt Staniszewski
Enviado el: viernes, 06 de marzo de 2009 23:04
Para: microblaze-uclinux@xxxxxxxxxxxxxx
Asunto: Re: [microblaze-uclinux] spi and spidev usage

 

Hi Carsten,

I tried out an oscilloscope today to see what kind of output I am getting from my SPI interface.  When I boot the board, all lines (MOSI, SCK, SS) are low.  When spidev initializes, then MOSI and SS go high whle SCK remains low constantly.  It seems to be setting some things, but I don't see a clock, so I'm not sending out data.

I've used the settings for clock polarity and phase from an earlier EDK project that uses SPI on this board.  I've based my max frequency on the clock to OPB SPI ratio in EDK.

Do you have any suggestions?

Thanks.

Matt