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Re: [microblaze-uclinux] spi and spidev usage
Sorry for take several weeks to get back to your last reply. I have been taking exams and on traveling.
Unfortunately I don't remember what the SCLK does when idle. The
other lines high is good and I would expect SCLK to do the same. When starting
a transmission first SS for one device goes low, later clock and data appear.
If SS and data are missing too I would look for the driver. If only clock is
missing you might rather look for hardware or FPGA-configuration.
When you say look for the hardware or FPGA-configuration, what do you suggest I specifically check? I've checked all my hardware settings against a working EDK project I have where I used the SPI core (without uCLInux).
You can test the SPI-core without linux. There is an example in
Xilinx-ISE (I used xps_intr_example.c). It is a loopback test but if you remove
the loopback option and add a call to XSpi_SetSlaveSelect before Transfer you
can see the output.
Do you mean xspi_intr_example? I found a version under my ISE directory. I've already tested the SPI core without linux using a previous project and it works just fine. However, in that program I use calls to XIO_Out32 at the certain memory addresses for the SPI core. Do you think using the XSpi example script could give a different result?
I'm using an old SPI-core (1.11a). I don't know if there is a driver-problem
with the new one or if the behavior is different.
I checked my SPI IP core, and I have the OPB SPI core version 1.00e. Is my version older than yours? I'm using Xilinx ISE 9.1i and according to Xilinx's download site, I have the latest IP core service pack.