Re: [microblaze-uclinux] Microblaze highest frequency.

[Nicolas Herve <nicolas.herve@xxxxxxxxx>]

2009/5/27 Andreas Hofmann <ahofmann@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>:
> [...]
> What maximum delay does your synthesis run report?


I mean the system clock (indeed the "Processor-Bus clock frequency")
still is at 100MHz, and have selected the 400 MHz for the CPU only in
the bsbwizard (at least, I though it wat, indeed it is named
"Reference Clock Frequency"). Compilation success with the Xplorer
Scripts option [1] without any complaint.
Then I presume that the CPU is configured for 400 MHz clock frequency.

After have a look in the synthesis/microblaze_0_wrapper_xst.srp
generated file I found the following :

> Timing Summary:
> ---------------
> Speed Grade: -10
>
>   Minimum period: 8.832ns (Maximum Frequency: 113.225MHz)
>   Minimum input arrival time before clock: 5.536ns
>   Maximum output required time after clock: 5.922ns
>   Maximum combinational path delay: 3.994ns

Is it just for the wrapper ?
and in synthesis/system_xst.srp I have:

> Timing Summary:
> ---------------
> Speed Grade: -10
>
>   Minimum period: 3.274ns (Maximum Frequency: 305.446MHz)
>   Minimum input arrival time before clock: 2.583ns
>   Maximum output required time after clock: 6.921ns
>   Maximum combinational path delay: No path found


I am a bit confused ...


[1] - in Menu:Project -> Project Option, "Hierarchy and Flow" tab,
"Effort Level to Run Implementation Tools" list. And I let the "Treat
timing closure as an error" to be sure.
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