Re: [microblaze-uclinux] "Found romfs @... klimit" message during kernel boot

["Victor G." <vga9@xxxxxx>]

On Mon, Jul 13, 2009 at 4:26 AM, Michal Simek<michal.simek@xxxxxxxxxxxxx> wrote:
> Hi,
>
> 1. turn on caches
> 2. send your mhs file () the best is petalinux-send-configs script output.
> 3. trace __log_buf where are kernel messages
>
> Thanks,
> Michal
>
> Victor G. wrote:
>> Hi,
>>
>> Instead of the regular startup messages, I am receiving the following
>> over uart when booting kernel from SDRAM:
>> Found romfs @ 0x901b108c (0x000f7000)
>> #### klimit 901c9000 ####
>> Moving 0x000f7000 bytes from 0x901b108c to 0x901c8868
>> New klimit: 0x902c0000
>>
>> Could please someone explain it?
>>
>> My system does not have flash yet. It is running on XUP-V2Pro and I am
>> using EDK 10.1 SP3 with petalinux-v0.40-rc3.
>>
>> What I have done so far:
>> * I have tried uploading kernel via xmd
>>
>> # Uploaded bitstream using xps or "impact -batch etc/download.cmd"
>>
>> # XMD kernel upload to SDRAM starting at 0x90000000
>> XMD% connect mb mdm -cable type xilinx_platformusb port usb21
>> XMD% dow -data ../../../software/petalinux-dist/images/image.bin 0x90000000
>> XMD% rst
>> XMD% con 0x90000000
>>
>> * I also tried using images/linux.bin instead of images/image.bin (using XMD)
>> However, I think linux.bin applies to only MMU supported builds with
>> INITRAMFS, isn't it? It looks as I have ROMFS. I am using the default
>> configuration without MMU enabled (Processor type and features -> MMU
>> support is unchecked in menuconfig).
>>
>> * I also uploaded images/image.bin via XMD to SDRAM and jumped to it
>> via u-boot's "go" command in addition to the regular "xmd>: con
>> 0x90000000" jump. In this case I uploaded u-boot manually using
>> FS-Boot and a serial send of u-boot.srec file.
>>
>> * Here is my FS-Boot log as well. I am not sure whether the "default
>> boot location" message makes any difference.
>>
>> FS-Waiting for SREC image....
>> FS-BOOT: Image download successful.
>> FS-BOOT: Warning image location differ from default boot location.
>> Image will not boot automatically after POR.
>> FS-BOOT: Booting image...
>> SDRAM:
>>   Enabling caches:
>>     Icache:FAIL
>>     Dcache:FAIL
>>     U-Boot Start: 0x9ffc0000
>>     Malloc Start: 0x9ff80000
>>  ... etc
>> Using default environment
>> ... etc
>>
>> Thanks,
>> Victor
>> ___________________________
>> microblaze-uclinux mailing list
>> microblaze-uclinux@xxxxxxxxxxxxxx
>> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
>> Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>>
>>
>
> --
> Michal Simek, Ing. (M.Eng)
> PetaLogix - Linux Solutions for a Reconfigurable World
> w: www.petalogix.com p: +61-7-30090663,+42-0-721842854 f: +61-7-30090663
> ___________________________
> microblaze-uclinux mailing list
> microblaze-uclinux@xxxxxxxxxxxxxx
> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>

Hi Michal,

1. I will be able to do later in the day
3. I've seen trace somewhere before; please let me know the details.
I'll do it tonight as well.
but for now...
2. Output of petalinux-send-configs and system.mhs

#SYSTEM CONFIGS
CONFIG_DEFAULTS_XILINX=y
CONFIG_DEFAULTS_XILINX_XILINX_XUP_V2PRO=y
CONFIG_DEFAULTS_KERNEL_2_6=y
CONFIG_DEFAULTS_LIBC_NONE=y
CONFIG_VENDOR=Xilinx
CONFIG_PRODUCT=Xilinx-XUP-V2Pro
CONFIG_LINUXDIR=linux-2.6.x
CONFIG_LIBCDIR=


#KERNEL CONFIGS
CONFIG_MICROBLAZE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_UID16=y
CONFIG_DEFCONFIG_LIST="arch/$ARCH/defconfig"
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_SYSFS_DEPRECATED=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_PRINTK=y
CONFIG_ELF_CORE=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=1
CONFIG_BLOCK=y
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_CFQ=y
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_PLATFORM_XILINX_XILINX_XUP_V2PRO=y
CONFIG_PROJECT_NAME="XUP-V2Pro"
CONFIG_UARTLITE=1
CONFIG_STDINOUT_BASEADDR=0x84000000
CONFIG_XILINX_ERAM_START=0x90000000
CONFIG_XILINX_ERAM_SIZE=0x10000000
CONFIG_XILINX_LMB_START=0x00000000
CONFIG_XILINX_LMB_SIZE=0x00002000
CONFIG_XILINX_CPU_CLOCK_FREQ=100000000
CONFIG_XILINX_MICROBLAZE0_INSTANCE="microblaze_0"
CONFIG_XILINX_MICROBLAZE0_SCO=0
CONFIG_XILINX_MICROBLAZE0_DATA_SIZE=32
CONFIG_XILINX_MICROBLAZE0_DYNAMIC_BUS_SIZING=1
CONFIG_XILINX_MICROBLAZE0_FAMILY="virtex2p"
CONFIG_XILINX_MICROBLAZE0_AREA_OPTIMIZED=0
CONFIG_XILINX_MICROBLAZE0_INTERCONNECT=1
CONFIG_XILINX_MICROBLAZE0_DPLB_DWIDTH=64
CONFIG_XILINX_MICROBLAZE0_DPLB_NATIVE_DWIDTH=32
CONFIG_XILINX_MICROBLAZE0_DPLB_BURST_EN=0
CONFIG_XILINX_MICROBLAZE0_DPLB_P2P=0
CONFIG_XILINX_MICROBLAZE0_IPLB_DWIDTH=64
CONFIG_XILINX_MICROBLAZE0_IPLB_NATIVE_DWIDTH=32
CONFIG_XILINX_MICROBLAZE0_IPLB_BURST_EN=0
CONFIG_XILINX_MICROBLAZE0_IPLB_P2P=0
CONFIG_XILINX_MICROBLAZE0_D_PLB=1
CONFIG_XILINX_MICROBLAZE0_D_OPB=0
CONFIG_XILINX_MICROBLAZE0_D_LMB=1
CONFIG_XILINX_MICROBLAZE0_I_PLB=1
CONFIG_XILINX_MICROBLAZE0_I_OPB=0
CONFIG_XILINX_MICROBLAZE0_I_LMB=1
CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_BARREL=0
CONFIG_XILINX_MICROBLAZE0_USE_DIV=0
CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
CONFIG_XILINX_MICROBLAZE0_USE_FPU=0
CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS=0
CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_IPLB_BUS_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_DPLB_BUS_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_FSL_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_PVR=0
CONFIG_XILINX_MICROBLAZE0_PVR_USER1=0x00000000
CONFIG_XILINX_MICROBLAZE0_PVR_USER2=0x00000000
CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED=1
CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PC_BRK=1
CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK=0
CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK=0
CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE=0
CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE=1
CONFIG_XILINX_MICROBLAZE0_RESET_MSR=0x00000000
CONFIG_XILINX_MICROBLAZE0_OPCODE_0X0_ILLEGAL=0
CONFIG_XILINX_MICROBLAZE0_FSL_LINKS=0
CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE=32
CONFIG_XILINX_MICROBLAZE0_USE_EXTENDED_FSL_INSTR=0
CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR=0x00000000
CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR=0x3FFFFFFF
CONFIG_XILINX_MICROBLAZE0_USE_ICACHE=0
CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR=1
CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS=0
CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE=8192
CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL=1
CONFIG_XILINX_MICROBLAZE0_ICACHE_LINE_LEN=4
CONFIG_XILINX_MICROBLAZE0_ICACHE_ALWAYS_USED=0
CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR=0x00000000
CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR=0x3FFFFFFF
CONFIG_XILINX_MICROBLAZE0_USE_DCACHE=0
CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR=1
CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG=0
CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE=8192
CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL=1
CONFIG_XILINX_MICROBLAZE0_DCACHE_LINE_LEN=4
CONFIG_XILINX_MICROBLAZE0_DCACHE_ALWAYS_USED=0
CONFIG_XILINX_MICROBLAZE0_USE_MMU=0
CONFIG_XILINX_MICROBLAZE0_MMU_DTLB_SIZE=4
CONFIG_XILINX_MICROBLAZE0_MMU_ITLB_SIZE=2
CONFIG_XILINX_MICROBLAZE0_MMU_TLB_ACCESS=3
CONFIG_XILINX_MICROBLAZE0_MMU_ZONES=16
CONFIG_XILINX_MICROBLAZE0_USE_INTERRUPT=1
CONFIG_XILINX_MICROBLAZE0_USE_EXT_BRK=1
CONFIG_XILINX_MICROBLAZE0_USE_EXT_NM_BRK=1
CONFIG_XILINX_MICROBLAZE0_HW_VER="7.10.d"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE="dlmb_cntlr"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR=0x00000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR=0x00001FFF
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK=0x80000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER="2.10.a"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE="ilmb_cntlr"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR=0x00000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR=0x00001FFF
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK=0x80000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER="2.10.a"
CONFIG_XILINX_UARTLITE_0_INSTANCE="RS232_Uart_1"
CONFIG_XILINX_UARTLITE_0_FAMILY="virtex2p"
CONFIG_XILINX_UARTLITE_0_SPLB_CLK_FREQ_HZ=100000000
CONFIG_XILINX_UARTLITE_0_BASEADDR=0x84000000
CONFIG_XILINX_UARTLITE_0_HIGHADDR=0x8400FFFF
CONFIG_XILINX_UARTLITE_0_SPLB_AWIDTH=32
CONFIG_XILINX_UARTLITE_0_SPLB_DWIDTH=64
CONFIG_XILINX_UARTLITE_0_SPLB_P2P=0
CONFIG_XILINX_UARTLITE_0_SPLB_MID_WIDTH=1
CONFIG_XILINX_UARTLITE_0_SPLB_NUM_MASTERS=2
CONFIG_XILINX_UARTLITE_0_SPLB_SUPPORT_BURSTS=0
CONFIG_XILINX_UARTLITE_0_SPLB_NATIVE_DWIDTH=32
CONFIG_XILINX_UARTLITE_0_BAUDRATE=115200
CONFIG_XILINX_UARTLITE_0_DATA_BITS=8
CONFIG_XILINX_UARTLITE_0_USE_PARITY=0
CONFIG_XILINX_UARTLITE_0_ODD_PARITY=0
CONFIG_XILINX_UARTLITE_0_HW_VER="1.00.a"
CONFIG_XILINX_UARTLITE_0_IRQ=2
CONFIG_XILINX_MDM_0_INSTANCE="debug_module"
CONFIG_XILINX_MDM_0_FAMILY="virtex2p"
CONFIG_XILINX_MDM_0_JTAG_CHAIN=2
CONFIG_XILINX_MDM_0_INTERCONNECT=1
CONFIG_XILINX_MDM_0_BASEADDR=0x84400000
CONFIG_XILINX_MDM_0_HIGHADDR=0x8440FFFF
CONFIG_XILINX_MDM_0_SPLB_AWIDTH=32
CONFIG_XILINX_MDM_0_SPLB_DWIDTH=64
CONFIG_XILINX_MDM_0_SPLB_P2P=0
CONFIG_XILINX_MDM_0_SPLB_MID_WIDTH=1
CONFIG_XILINX_MDM_0_SPLB_NUM_MASTERS=2
CONFIG_XILINX_MDM_0_SPLB_NATIVE_DWIDTH=32
CONFIG_XILINX_MDM_0_SPLB_SUPPORT_BURSTS=0
CONFIG_XILINX_MDM_0_OPB_DWIDTH=32
CONFIG_XILINX_MDM_0_OPB_AWIDTH=32
CONFIG_XILINX_MDM_0_MB_DBG_PORTS=1
CONFIG_XILINX_MDM_0_USE_UART=1
CONFIG_XILINX_MDM_0_UART_WIDTH=8
CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS=0
CONFIG_XILINX_MDM_0_HW_VER="1.00.d"
CONFIG_XILINX_ETHERNETLITE_0_INSTANCE="Ethernet_MAC"
CONFIG_XILINX_ETHERNETLITE_0_FAMILY="virtex2p"
CONFIG_XILINX_ETHERNETLITE_0_BASEADDR=0x81000000
CONFIG_XILINX_ETHERNETLITE_0_HIGHADDR=0x8100FFFF
CONFIG_XILINX_ETHERNETLITE_0_SPLB_CLK_PERIOD_PS=10000
CONFIG_XILINX_ETHERNETLITE_0_SPLB_AWIDTH=32
CONFIG_XILINX_ETHERNETLITE_0_SPLB_DWIDTH=64
CONFIG_XILINX_ETHERNETLITE_0_SPLB_P2P=0
CONFIG_XILINX_ETHERNETLITE_0_SPLB_MID_WIDTH=1
CONFIG_XILINX_ETHERNETLITE_0_SPLB_NUM_MASTERS=2
CONFIG_XILINX_ETHERNETLITE_0_SPLB_NATIVE_DWIDTH=32
CONFIG_XILINX_ETHERNETLITE_0_SPLB_SUPPORT_BURSTS=0
CONFIG_XILINX_ETHERNETLITE_0_DUPLEX=1
CONFIG_XILINX_ETHERNETLITE_0_TX_PING_PONG=0
CONFIG_XILINX_ETHERNETLITE_0_RX_PING_PONG=0
CONFIG_XILINX_ETHERNETLITE_0_HW_VER="2.00.b"
CONFIG_XILINX_ETHERNETLITE_0_IRQ=1
CONFIG_XILINX_TIMER_0_INSTANCE="xps_timer_1"
CONFIG_XILINX_TIMER_0_FAMILY="virtex2p"
CONFIG_XILINX_TIMER_0_COUNT_WIDTH=32
CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY=0
CONFIG_XILINX_TIMER_0_TRIG0_ASSERT=1
CONFIG_XILINX_TIMER_0_TRIG1_ASSERT=1
CONFIG_XILINX_TIMER_0_GEN0_ASSERT=1
CONFIG_XILINX_TIMER_0_GEN1_ASSERT=1
CONFIG_XILINX_TIMER_0_BASEADDR=0x83C00000
CONFIG_XILINX_TIMER_0_HIGHADDR=0x83C0FFFF
CONFIG_XILINX_TIMER_0_SPLB_AWIDTH=32
CONFIG_XILINX_TIMER_0_SPLB_DWIDTH=64
CONFIG_XILINX_TIMER_0_SPLB_P2P=0
CONFIG_XILINX_TIMER_0_SPLB_MID_WIDTH=1
CONFIG_XILINX_TIMER_0_SPLB_NUM_MASTERS=2
CONFIG_XILINX_TIMER_0_SPLB_SUPPORT_BURSTS=0
CONFIG_XILINX_TIMER_0_SPLB_NATIVE_DWIDTH=32
CONFIG_XILINX_TIMER_0_HW_VER="1.00.a"
CONFIG_XILINX_TIMER_0_IRQ=0
CONFIG_XILINX_INTC_0_INSTANCE="xps_intc_0"
CONFIG_XILINX_INTC_0_FAMILY="virtex2p"
CONFIG_XILINX_INTC_0_BASEADDR=0x81800000
CONFIG_XILINX_INTC_0_HIGHADDR=0x8180FFFF
CONFIG_XILINX_INTC_0_SPLB_AWIDTH=32
CONFIG_XILINX_INTC_0_SPLB_DWIDTH=64
CONFIG_XILINX_INTC_0_SPLB_P2P=0
CONFIG_XILINX_INTC_0_SPLB_NUM_MASTERS=2
CONFIG_XILINX_INTC_0_SPLB_MID_WIDTH=1
CONFIG_XILINX_INTC_0_SPLB_NATIVE_DWIDTH=32
CONFIG_XILINX_INTC_0_SPLB_SUPPORT_BURSTS=0
CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS=3
CONFIG_XILINX_INTC_0_KIND_OF_INTR=0x00000006
CONFIG_XILINX_INTC_0_KIND_OF_EDGE=0x00000006
CONFIG_XILINX_INTC_0_KIND_OF_LVL=0x00000001
CONFIG_XILINX_INTC_0_HAS_IPR=1
CONFIG_XILINX_INTC_0_HAS_SIE=1
CONFIG_XILINX_INTC_0_HAS_CIE=1
CONFIG_XILINX_INTC_0_HAS_IVR=1
CONFIG_XILINX_INTC_0_IRQ_ACTIVE=1
CONFIG_XILINX_INTC_0_HW_VER="1.00.a"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES=2
CONFIG_XILINX_TIMER_NUM_INSTANCES=1
CONFIG_XILINX_MPMC_NUM_INSTANCES=1
CONFIG_XILINX_ETHERNETLITE_NUM_INSTANCES=1
CONFIG_XILINX_INTC_NUM_INSTANCES=1
CONFIG_XILINX_MDM_NUM_INSTANCES=1
CONFIG_XILINX_UARTLITE_NUM_INSTANCES=1
CONFIG_NO_MMU=y
CONFIG_LARGE_ALLOCS=y
CONFIG_CMDLINE=""
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_BINFMT_FLAT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM=y
CONFIG_INET=y
CONFIG_IP_FIB_HASH=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
CONFIG_MTD_UCLINUX=y
CONFIG_MTD_UCLINUX_EBSS=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
CONFIG_NETDEVICES=y
CONFIG_XILINX_EMACLITE=y
CONFIG_SERIAL_UARTLITE=y
CONFIG_SERIAL_UARTLITE_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_HW_RANDOM=y
CONFIG_XILINX_GPIO=y
CONFIG_FIRMWARE_EDID=y
CONFIG_XILINX_EDK=y
CONFIG_EXT2_FS=y
CONFIG_FS_POSIX_ACL=y
CONFIG_ROMFS_FS=y
CONFIG_DIRECTIO=y
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_RAMFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_MSDOS_PARTITION=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK_UARTLITE_ADDRESS=0x00000000
CONFIG_ZLIB_INFLATE=y
CONFIG_IOMAP_COPY=y


#USERLAND CONFIGS
CONFIG_SYSTEM_MAC_ADDRESS="00:0a:35:00:22:01"
CONFIG_SYSTEM_IP_ADDRESS="192.168.0.10"
CONFIG_SYSTEM_SERVERIP_ADDRESS="192.168.0.1"
CONFIG_SYSTEM_HOSTNAME="uclinux"
CONFIG_SYSTEM_ROOT_PASSWD="root"
CONFIG_SYSTEM_ROOTFS_CRAMFS=y
CONFIG_SYSTEM_COPY_TO_TFTPBOOT=y
CONFIG_SYSTEM_TFTPBOOT_DIR="/tftpboot"
CONFIG_SYSTEM_BUILD_UBOOT=y
CONFIG_SYSTEM_PARTITION1_NAME="boot"
CONFIG_SYSTEM_PARTITION1_SIZE=40000
CONFIG_SYSTEM_PARTITION2_NAME="bootenv"
CONFIG_SYSTEM_PARTITION2_SIZE=20000
CONFIG_SYSTEM_PARTITION3_NAME="config"
CONFIG_SYSTEM_PARTITION3_SIZE=20000
CONFIG_SYSTEM_PARTITION4_NAME="image"
CONFIG_SYSTEM_PARTITION4_SIZE=400000
CONFIG_SYSTEM_PARTITION5_NAME="spare"
CONFIG_SYSTEM_PARTITION5_SIZE=0
CONFIG_SYSTEM_PARTITION6_NAME=""
CONFIG_SYSTEM_PARTITION6_SIZE=0
CONFIG_USER_INIT_INIT=y
CONFIG_USER_OTHER_SH=y
CONFIG_USER_SASH_REBOOT=y
CONFIG_USER_SASH_SHUTDOWN=y
CONFIG_USER_VERSION_VERSION=y
CONFIG_USER_LOGIN_LOGIN=y
CONFIG_USER_AGETTY_AGETTY=y
CONFIG_USER_LOGIN_PASSWD=y
CONFIG_LIB_ZLIB_FORCE=y
CONFIG_USER_FLATFSD_FLATFSD=y
CONFIG_USER_FLATFSD_AUTO=y
CONFIG_USER_DHCPCD_NEW_DHCPCD=y
CONFIG_USER_FTPD_FTPD=y
CONFIG_USER_INETD_INETD=y
CONFIG_USER_PING_PING=y
CONFIG_USER_PORTMAP_PORTMAP=y
CONFIG_USER_TELNETD_TELNETD=y
CONFIG_USER_TELNETD_DOES_NOT_USE_OPENPTY=y
CONFIG_USER_THTTPD_THTTPD=y
CONFIG_USER_NET_TOOLS_HOSTNAME=y
CONFIG_USER_NET_TOOLS_IFCONFIG=y
CONFIG_USER_GPIO_TEST=y
CONFIG_USER_HD_HD=y
CONFIG_USER_FILEUTILS_CAT=y
CONFIG_USER_FILEUTILS_CHMOD=y
CONFIG_USER_FILEUTILS_CMP=y
CONFIG_USER_FILEUTILS_CP=y
CONFIG_USER_FILEUTILS_LN=y
CONFIG_USER_FILEUTILS_MKDIR=y
CONFIG_USER_FILEUTILS_MV=y
CONFIG_USER_FILEUTILS_RM=y
CONFIG_USER_FILEUTILS_TOUCH=y
CONFIG_USER_SHUTILS_BASENAME=y
CONFIG_USER_SHUTILS_DATE=y
CONFIG_USER_SHUTILS_ECHO=y
CONFIG_USER_SHUTILS_FALSE=y
CONFIG_USER_SHUTILS_PWD=y
CONFIG_USER_SHUTILS_TRUE=y
CONFIG_USER_SHUTILS_UNAME=y
CONFIG_USER_SYSUTILS_REBOOT=y
CONFIG_USER_SYSUTILS_SHUTDOWN=y
CONFIG_USER_SYSUTILS_FREE=y
CONFIG_USER_SYSUTILS_HOSTNAME=y
CONFIG_USER_SYSUTILS_KILL=y
CONFIG_USER_SYSUTILS_PS=y
CONFIG_USER_BUSYBOX_BUSYBOX=y
CONFIG_USER_BUSYBOX_DD=y
CONFIG_USER_BUSYBOX_GUNZIP=y
CONFIG_USER_BUSYBOX_GUNZIP_UNCOMPRESS=y
CONFIG_USER_BUSYBOX_IFCONFIG=y
CONFIG_USER_BUSYBOX_IFCONFIG_STATUS=y
CONFIG_USER_BUSYBOX_INSMOD=y
CONFIG_USER_BUSYBOX_LSMOD=y
CONFIG_USER_BUSYBOX_MODPROBE=y
CONFIG_USER_BUSYBOX_RMMOD=y
CONFIG_USER_BUSYBOX_2_6_MODULES=y
CONFIG_USER_BUSYBOX_KILL=y
CONFIG_USER_BUSYBOX_KILLALL=y
CONFIG_USER_BUSYBOX_LOGIN=y
CONFIG_USER_BUSYBOX_LS=y
CONFIG_USER_BUSYBOX_LS_USERNAME=y
CONFIG_USER_BUSYBOX_LS_TIMESTAMPS=y
CONFIG_USER_BUSYBOX_LS_FILETYPES=y
CONFIG_USER_BUSYBOX_LS_SORTFILES=y
CONFIG_USER_BUSYBOX_LS_RECURSIVE=y
CONFIG_USER_BUSYBOX_LS_FOLLOWLINKS=y
CONFIG_USER_BUSYBOX_MOUNT=y
CONFIG_USER_BUSYBOX_MOUNT_LOOP=y
CONFIG_USER_BUSYBOX_NFSMOUNT=y
CONFIG_USER_BUSYBOX_SHELL=y
CONFIG_USER_BUSYBOX_MSH=y
CONFIG_USER_BUSYBOX_SH_IS_MSH=y
CONFIG_USER_BUSYBOX_COMMAND_EDITING=y
CONFIG_USER_BUSYBOX_COMMAND_HISTORY=15
CONFIG_USER_BUSYBOX_COMMAND_SAVEHISTORY=y
CONFIG_USER_BUSYBOX_COMMAND_TAB_COMPLETION=y
CONFIG_USER_BUSYBOX_COMMAND_USERNAME_COMPLETION=y
CONFIG_USER_BUSYBOX_TAB_COMPLETION=y
CONFIG_USER_BUSYBOX_USERNAME_COMPLETION=y
CONFIG_USER_BUSYBOX_SH_STANDALONE_SHELL=y
CONFIG_USER_BUSYBOX_SH_APPLETS_ALWAYS_WIN=y
CONFIG_USER_BUSYBOX_SH_FANCY_PROMPT=y
CONFIG_USER_BUSYBOX_SH_EXTRA_QUIET=y
CONFIG_USER_BUSYBOX_TEST=y
CONFIG_USER_BUSYBOX_TRUE_FALSE=y
CONFIG_USER_BUSYBOX_UMOUNT=y
CONFIG_USER_BUSYBOX_MOUNT_FORCE=y
CONFIG_USER_BUSYBOX_UPTIME=y
CONFIG_USER_BUSYBOX_VI=y
CONFIG_USER_BUSYBOX_VI_COLON=y
CONFIG_USER_BUSYBOX_VI_YANKMARK=y
CONFIG_USER_BUSYBOX_VI_SEARCH=y
CONFIG_USER_BUSYBOX_VI_READONLY=y
CONFIG_USER_BUSYBOX_VI_SETOPTS=y
CONFIG_USER_BUSYBOX_VI_SET=y
CONFIG_USER_BUSYBOX_VI_WIN_RESIZE=y
CONFIG_USER_BUSYBOX_WGET=y
CONFIG_USER_BUSYBOX_WGET_STATUSBAR=y
CONFIG_USER_BUSYBOX_VERBOSE_USAGE=y
CONFIG_USER_BUSYBOX_AUTOWIDTH=y
CONFIG_USER_BUSYBOX_HUMAN_READABLE=y
CONFIG_USER_RAMIMAGE_NONE=y

---------------------------------------------------
system.mhs:


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Wed Jul  8 21:00:39 2009
# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
# Family:    virtex2p
# Device:    xc2vp30
# Package:   ff896
# Speed Grade:  -7
# Processor: microblaze_0
# System clock frequency: 100.00 MHz
# On Chip Memory :   8 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM = 256 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
 PORT fpga_0_Ethernet_MAC_slew1_pin = net_vcc, DIR = O
 PORT fpga_0_Ethernet_MAC_slew2_pin = net_vcc, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin =
fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin =
fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin =
fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin =
fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
 PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR =
O, VEC = [2:0]
 PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR
= O, VEC = [2:0]
 PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR =
O, VEC = [12:0]
 PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =
fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O,
VEC = [7:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [7:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [63:0]
 PORT fpga_0_net_gnd_pin = net_gnd, DIR = O
 PORT fpga_0_net_gnd_1_pin = net_gnd, DIR = O
 PORT fpga_0_net_gnd_2_pin = net_gnd, DIR = O
 PORT fpga_0_net_gnd_3_pin = net_gnd, DIR = O
 PORT fpga_0_net_gnd_4_pin = net_gnd, DIR = O
 PORT fpga_0_net_gnd_5_pin = net_gnd, DIR = O
 PORT fpga_0_net_gnd_6_pin = net_gnd, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER HW_VER = 7.10.d
 PARAMETER C_DEBUG_ENABLED = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 PORT MB_RESET = mb_reset
 PORT Interrupt = Interrupt
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.03.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
 PORT Interrupt = RS232_Uart_1_Interrupt
END

BEGIN xps_ethernetlite
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_SPLB_CLK_PERIOD_PS = 10000
 PARAMETER C_BASEADDR = 0x81000000
 PARAMETER C_HIGHADDR = 0x8100ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR_SDRAM
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_MEM_PARTNO = CUSTOM
 PARAMETER C_MEM_TYPE = DDR
 PARAMETER C_USE_STATIC_PHY = 1
 PARAMETER C_MEM_CLK_WIDTH = 3
 PARAMETER C_STATIC_PHY_RDEN_DELAY = 6
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
 PARAMETER C_MPMC_BASEADDR = 0x90000000
 PARAMETER C_MPMC_HIGHADDR = 0x9FFFFFFF
 PARAMETER C_MPMC_CTRL_BASEADDR = 0x84800000
 PARAMETER C_MPMC_CTRL_HIGHADDR = 0x8480ffff
 PARAMETER C_MEM_REG_DIMM = 0
 PARAMETER C_MEM_PART_DATA_DEPTH = 32
 PARAMETER C_MEM_PART_NUM_COL_BITS = 10
 PARAMETER C_MEM_PART_CAS_A_FMAX = 100
 PARAMETER C_MEM_PART_CAS_A = 2.5
 PARAMETER C_MEM_PART_TRAS = 60000
 PARAMETER C_MEM_PART_TRASMAX = 120000000
 PARAMETER C_MEM_PART_TRC = 90000
 PARAMETER C_MEM_PART_TWR = 20000
 PARAMETER C_MEM_PART_TRRD = 20000
 PARAMETER C_MEM_PART_TRCD = 30000
 PARAMETER C_MEM_PART_TREFI = 7800000
 PARAMETER C_MEM_PART_TRFC = 100000
 PARAMETER C_MEM_PART_TRP = 30000
 BUS_INTERFACE SPLB0 = mb_plb
 BUS_INTERFACE MPMC_CTRL = mb_plb
 PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
 PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
 PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
 PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
 PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
 PORT MPMC_Clk0 = sys_clk_s
 PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
 PORT MPMC_Clk_Mem = DDR_SDRAM_MPMC_Clk_Mem
 PORT MPMC_Rst = sys_periph_reset
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Interrupt = xps_timer_1_Interrupt
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = DCM0
 PARAMETER C_CLKOUT1_FREQ = 100000000
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT1_PHASE = 90
 PARAMETER C_CLKOUT1_GROUP = DCM0
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT2_PHASE = 20
 PARAMETER C_CLKOUT2_GROUP = NONE
 PARAMETER C_CLKIN_BUF = FALSE
 PORT CLKOUT0 = sys_clk_s
 PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s
 PORT CLKOUT2 = DDR_SDRAM_MPMC_Clk_Mem
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 1.00.d
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Irq = Interrupt
 PORT Intr = RS232_Uart_1_Interrupt & Ethernet_MAC_IP2INTC_Irpt &
xps_timer_1_Interrupt
END

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