[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[microblaze-uclinux] Microblaze with mmu support - "system reset" after u-boot attempts to load kernel

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] Microblaze with mmu support - "system reset" after u-boot attempts to load kernel
From: hoefle marco <marco.hoefle@xxxxxxxxxxxxx>
Date: Mon, 31 Aug 2009 16:05:19 +0200
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxxxxxxxx
Hallo,
I want to test petalinux with mmu support. The reason is to have
programs running which use mmu specific system calls (fork() etc.).
One thing I came across was to figure out which mmu type is needed
(protection, virtual...). I am on a Spartan 3A 700 so I am tight on
logic resources.
For now I took the same as on a reference design, C_USE_MMU = 2.
I read in another thread that mmu or no mmu will not increase the system
performance, but as I had to deselect "optimze area" in the microblaze
settings I hope I get some improvement.
The design fits into the fpga (memory test passes) and the images could
be built.
However, after u-boot attempts to start the kernel the system behaves as
if somebody pressed the reset button. The petalogix first stage
bootloader runs again and loads u-boot. After the bootdelay the same
thing happens again.
I took the settings from a working non-mmu design for the kernel and the
user space things. The memory map for the memories remained the same. I
just switches on mmu support.
I attached the relevant parts of the kernel config as well as of the mhs
file.
Thanks for any hints,
Marco




Kernel config:
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.20-uc0
#
CONFIG_MICROBLAZE=y
# CONFIG_SWAP is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
# CONFIG_GENERIC_TIME is not set
CONFIG_UID16=y
CONFIG_DEFCONFIG_LIST="arch/$ARCH/defconfig-mmu"

#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32

#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
# CONFIG_HOTPLUG is not set
CONFIG_PRINTK=y
# CONFIG_BUG is not set
CONFIG_ELF_CORE=y
# CONFIG_BASE_FULL is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
CONFIG_SHMEM=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=1
# CONFIG_SLOB is not set

#
# Boot options
#
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_FORCE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set

#
# Exectuable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set

#
# Advanced setup
#
# CONFIG_ADVANCED_OPTIONS is not set

#
# Default settings for advanced configuration options are used
#
CONFIG_HIGHMEM_START=0xfe000000
CONFIG_LOWMEM_SIZE=0x30000000
CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_BOOT_LOAD=0x00800000









relevant things from MHS file:

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 7.10.d
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0xA0000000
 PARAMETER C_ICACHE_HIGHADDR = 0xA3FFFFFF
 PARAMETER C_DCACHE_BASEADDR = 0xA0000000
 PARAMETER C_DCACHE_HIGHADDR = 0xA3FFFFFF
 PARAMETER C_FAMILY = spartan3a
 PARAMETER C_INSTANCE = microblaze_0
 PARAMETER C_USE_PCMP_INSTR = 0
 PARAMETER C_USE_MMU = 2
 PARAMETER C_USE_BARREL = 1
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE ixcl = ixcl
 BUS_INTERFACE dxcl = dxcl
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 PORT MB_RESET = mb_reset
 PORT Interrupt = Interrupt
END


BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_DCE
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_SPLB_CLK_FREQ_HZ = 62500000
 PARAMETER C_BASEADDR = 0x81000000
 PARAMETER C_HIGHADDR = 0x810FFFFF
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = RS232_DCE_RX
 PORT TX = RS232_DCE_TX
 PORT Interrupt = RS232_DCE_Interrupt
END

BEGIN xps_ethernetlite
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_SPLB_CLK_PERIOD_PS = 16000
 PARAMETER C_BASEADDR = 0x80000000
 PARAMETER C_HIGHADDR = 0x800FFFFF
 BUS_INTERFACE SPLB = mb_plb
 PORT PHY_col = Ethernet_MAC_PHY_col
 PORT PHY_crs = Ethernet_MAC_PHY_crs
 PORT PHY_rst_n = Ethernet_MAC_PHY_rst_n
 PORT PHY_rx_clk = Ethernet_MAC_PHY_rx_clk
 PORT PHY_dv = Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = Ethernet_MAC_PHY_rx_data
 PORT PHY_rx_er = Ethernet_MAC_PHY_rx_er
 PORT PHY_tx_clk = Ethernet_MAC_PHY_tx_clk
 PORT PHY_tx_en = Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_data = Ethernet_MAC_PHY_tx_data
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR2_SDRAM
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_NUM_PORTS = 3
 PARAMETER C_PIM0_BASETYPE = 1
 PARAMETER C_PIM1_BASETYPE = 1
 PARAMETER C_MEM_PARTNO = MT47H32M16-3
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_SPECIAL_BOARD = S3A_STKIT
 PARAMETER C_XCL0_WRITEXFER = 0
 PARAMETER C_PIM2_BASETYPE = 2
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 8000
 PARAMETER C_SPLB2_NATIVE_DWIDTH = 32
 PARAMETER C_MPMC_BASEADDR = 0xA0000000
 PARAMETER C_MPMC_HIGHADDR = 0xA3FFFFFF
 PARAMETER C_PI0_RD_FIFO_TYPE = SRL
 PARAMETER C_PI0_WR_FIFO_TYPE = SRL
 PARAMETER C_PI1_RD_FIFO_TYPE = SRL
 PARAMETER C_PI1_WR_FIFO_TYPE = SRL
 PARAMETER C_PI2_RD_FIFO_TYPE = SRL
 PARAMETER C_PI2_WR_FIFO_TYPE = SRL
 BUS_INTERFACE XCL0 = ixcl
 BUS_INTERFACE XCL1 = dxcl
 BUS_INTERFACE SPLB2 = mb_plb
 PORT DDR2_ODT = DDR2_SDRAM_DDR2_ODT
 PORT DDR2_Addr = DDR2_SDRAM_DDR2_Addr
 PORT DDR2_BankAddr = DDR2_SDRAM_DDR2_BankAddr
 PORT DDR2_CAS_n = DDR2_SDRAM_DDR2_CAS_n
 PORT DDR2_RAS_n = DDR2_SDRAM_DDR2_RAS_n
 PORT DDR2_CE = DDR2_SDRAM_DDR2_CE
 PORT DDR2_CS_n = DDR2_SDRAM_DDR2_CS_n
 PORT DDR2_WE_n = DDR2_SDRAM_DDR2_WE_n
 PORT DDR2_Clk = DDR2_SDRAM_DDR2_Clk
 PORT DDR2_Clk_n = DDR2_SDRAM_DDR2_Clk_n
 PORT DDR2_DM = DDR2_SDRAM_DDR2_DM
 PORT DDR2_DQS = DDR2_SDRAM_DDR2_DQS
 PORT DDR2_DQS_n = DDR2_SDRAM_DDR2_DQS_n
 PORT DDR2_DQ = DDR2_SDRAM_DDR2_DQ
 PORT DDR2_DQS_Div_I = DDR2_SDRAM_DDR2_DQS_Div_I
 PORT DDR2_DQS_Div_O = DDR2_SDRAM_DDR2_DQS_Div_O
 PORT MPMC_Clk0 = DDR2_SDRAM_mpmc_clk_s
 PORT MPMC_Clk90 = DDR2_SDRAM_mpmc_clk_90_s
 PORT MPMC_Rst = sys_periph_reset
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = FLASH
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_NUM_CHANNELS = 0
 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 16000
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 70000
 PARAMETER C_TWC_PS_MEM_0 = 70000
 PARAMETER C_TAVDV_PS_MEM_0 = 70000
 PARAMETER C_TWP_PS_MEM_0 = 45000
 PARAMETER C_THZCE_PS_MEM_0 = 25000
 PARAMETER C_THZOE_PS_MEM_0 = 25000
 PARAMETER C_TLZWE_PS_MEM_0 = 5000
 PARAMETER C_MEM0_BASEADDR = 0xB0000000
 PARAMETER C_MEM0_HIGHADDR = 0xB03FFFFF
 BUS_INTERFACE SPLB = mb_plb
 PORT Mem_A = FLASH_Mem_A_split
 PORT Mem_DQ = FLASH_Mem_DQ
 PORT Mem_OEN = FLASH_Mem_OEN
 PORT Mem_WEN = FLASH_Mem_WEN
 PORT Mem_CEN = FLASH_Mem_CEN
 PORT RdClk = sys_clk_s
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 1
 PARAMETER C_BASEADDR = 0x41000000
 PARAMETER C_HIGHADDR = 0x410FFFFF
 BUS_INTERFACE SPLB = mb_plb
 PORT Interrupt = xps_timer_1_Interrupt
END



BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x400FFFFF
 BUS_INTERFACE SPLB = mb_plb
 PORT Irq = Interrupt
 PORT Intr = RS232_DCE_Interrupt & Ethernet_MAC_IP2INTC_Irpt &
xps_timer_1_Interrupt
END



___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
Prev by Date: Re: [microblaze-uclinux] newbie question on xilinx_ll_temac.c u-boot driver
Next by Date: [microblaze-uclinux] reference design for nuHorizons Spartan 3 Board
Previous by thread: [microblaze-uclinux] Changing from S3E500 to 1600
Next by thread: [microblaze-uclinux] reference design for nuHorizons Spartan 3 Board
Index(es):
- Date
- Thread