[microblaze-uclinux] Using Xilinx Central DMA

[Thomas D Tessier <tomt@xxxxxxxxx>]

All,

Been through quite a bit of documentation but it still isn't clear.  I 
have a simple FIFO (RDpFIFO) in my own IP block.  I want to be able to 
do a burst read of the data out of this FIFO as the element that fills 
it cannot be held off.  A simple register read loop just doesn't work 
for the amount and timeframe we have available.  And we don't seem to be 
able to do a burst read from the same memory location?

So Central DMA to the rescue, so I thought.  My first attempt was to 
attach the Slave Port to the same PLB of my IP block and the Master to a 
new (dedicated) PLB port on my DDR controller? Well the design wouldn't 
boot.  Next I tried the Slave and Master ports to the same PLB bus, the 
DDR controller is also hanging off of this bus.  Again wouldn't boot.

So I have two questions:
1) What is the preferred hardware configuration (I am experimenting on a 
1800ADSP board; the real hardware is somewhat different, but not that 
much different).
2) After I get the hardware behaving how do I really access the DMA 
engine from the S/W. Searched the list and nothing really concrete 
turned up.  I am using Petalinux Version 0.30-rc1

Thanks in advance,
TomT...

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: t2design                                                             :
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