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Re: [microblaze-uclinux] Using Xilinx Central DMA



John,

Thanks for the insight. I do have it working and wanted to give the group some feedback.

1) The Central DMA can be connected to the same PLB for Master and Slave.
2) If you are going to read from your own designed IP which is attached as a PLB Slave than this Slave must support Burst Mode transfers (something I missed). 3) You could configure the Central DMA to have it's own Slave Port to the DDR controller, I didn't have success doing this but may revisit it.

Thanks again for the helpful suggestions,
TomT...

John Williams wrote:
Hi Tom,

On Tue, Sep 22, 2009 at 11:37 AM, Thomas D Tessier <tomt@xxxxxxxxx> wrote:

Been through quite a bit of documentation but it still isn't clear.  I have
a simple FIFO (RDpFIFO) in my own IP block.  I want to be able to do a burst
read of the data out of this FIFO as the element that fills it cannot be
held off.  A simple register read loop just doesn't work for the amount and
timeframe we have available.  And we don't seem to be able to do a burst
read from the same memory location?

So Central DMA to the rescue, so I thought.  My first attempt was to attach
the Slave Port to the same PLB of my IP block and the Master to a new
(dedicated) PLB port on my DDR controller? Well the design wouldn't boot.
 Next I tried the Slave and Master ports to the same PLB bus, the DDR
controller is also hanging off of this bus.  Again wouldn't boot.

The MPLB port of the central_dma should connect to the PLB bus on
which the DMA targetted memory and devices exists.

The SPLB port should connect to the PLB bus through which the
MicroBlaze will control the DMA (issue transfer commands etc).
Typically , these will be the same in a single-bus system.

It sounds like you did this in attempt 2, and got a dead config.
Check for timing errors out of PAR etc.  Also comfigure the FPGA,
connect with XMD and do basic HW liveness tests - memory read/write,
uart read/write etc.  Also make sure you haven't exceeded any rules
about max PLB masters or slaves.  If you do, you'll have to trunk your
PLB, add bridges etc.

So I have two questions:
1) What is the preferred hardware configuration (I am experimenting on a
1800ADSP board; the real hardware is somewhat different, but not that much
different).

I think you're on the right track here.  I'd be verifying all of this
in XMD, and with little standalone apps, before trying to get it going
in Linux.

2) After I get the hardware behaving how do I really access the DMA engine
from the S/W. Searched the list and nothing really concrete turned up.  I am
using Petalinux Version 0.30-rc1

There's no linux driver for the xps_central_dma controller.  you have
a few options - if you are happy to limit the use of this DMA
controller to just your IP core, then you can safely have your device
driver bang on the central DMA directly to do its thing.

If you want to make the DMA controller more widely visible and useable
in the system, then you have to write a generic driver for it, then
hook your IP core driver into that.  Probably more than you need right
now.

Hope this helps,

John


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