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[microblaze-uclinux] Peripheral instance DDR2_SDRAM is not a valid IP for PARAMETER main_memory !

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] Peripheral instance DDR2_SDRAM is not a valid IP for PARAMETER main_memory !
From: Victor Gusev <vga9@xxxxxx>
Date: Mon, 26 Oct 2009 01:17:17 -0700
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxxxxxxxx

Hi,

I am adapting Spartan3E1600's design to ML505 board using EDK 9.2i. The older version is required to support special utilities developed for it. I did a number of changes to the provided example from the user-platforms folder including the DDR ram update to DDR2. As a reference I am using the Xilinx-ML505-ll_temac-sgdma-edk101 example that I got working earlier. Here is the error I receive in EDK 9.2i while making the libraries:

Question 1:
//petalinux-v0.40-rc4/hardware/user-platforms/Xilinx
-Spartan3E1600-RevA-edk92_boardchange/system.mss line 12 - Peripheral
instance DDR2_SDRAM is not a valid IP for PARAMETER main_memory !

What am I missing?

I checked //petalinux-v0.40-rc4/hardware/edk_user_repository/PetaLogix/bsp/petalinux_v1_00_b/data/petalinux_v2_1_0.mld file and found mpmc controller in the 'range=' list. I am using MPMC 3.00.a. Previously it complained that the main_memory PARAMETER was missing so I added the DDR2_SDRAM to the OS part of the MSS file (i.e. PARAMETER main_memory = DDR2_SDRAM).

petalinux_v2_1_0.mld:
PARAMETER name = main_memory, desc ="Name of Main Memory used with PetaLinux", type = peripheral_instance, range=(opb_ddr,opb_emc,plb_ddr,plb_emc,opb_sdram,plb_sdram,mch_opb_sdram,mch_opb_ddr, mch_opb_ddr2, mch_opb_emc, plb_ddr2, mpmc), default = none;

Because petalinux_v1_00_b referred to standalone_v2_00_a BSP that 9.2i does not have, I had to switch to petalinux_v1_00_a that supports //Xilinx/9.2i/edk/sw/lib/bsp/standalone_v1_00_a/. By the way this is another question (Question 2): whether it is possible to run EDK 9.2i and still use petalinux_v1_00_b (i.e. for 2.6 kernel support)?

Thanks,
Victor

Here is my MHS file:
-------------------------------------------------------------
PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_DTE_RX_pin = fpga_0_RS232_DTE_RX, DIR = I
PORT fpga_0_RS232_DTE_TX_pin = fpga_0_RS232_DTE_TX, DIR = O
PORT fpga_0_FLASH_emc_ben_gnd_pin = net_gnd, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr, DIR = O, VEC = [12:0]
PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_DDR2_BankAddr, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_n, DIR = O
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM, DIR = O, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk, DIR = O, VEC = [1:0], SIGIS = CLK
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_n, DIR = O, VEC = [1:0], SIGIS = CLK
PORT fpga_0_DDR2_SDRAM_DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ, DIR = IO, VEC = [63:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS, DIR = IO, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT, DIR = O, VEC = [1:0]
PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC = [7:30]
PORT fpga_0_FLASH_Mem_DQ = fpga_0_FLASH_Mem_DQ, DIR = IO, VEC = [0:7]
PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O
PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O, VEC = [0:0]
PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O, VEC = [0:0]
PORT fpga_0_FLASH_Mem_ADV_LDN_pin = fpga_0_FLASH_Mem_ADV_LDN, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_n, DIR = O
PORT ExternalPort_0 = net_ExternalPort_0, DIR = O, VEC = [0:1]

BEGIN microblaze
PARAMETER HW_VER = 7.00.a
PARAMETER INSTANCE = microblaze_0
PARAMETER C_USE_ICACHE = 1
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0x20000000
PARAMETER C_ICACHE_HIGHADDR = 0x2fffffff
PARAMETER C_DCACHE_BASEADDR = 0x20000000
PARAMETER C_DCACHE_HIGHADDR = 0x2fffffff
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_HW_MUL = 2
PARAMETER C_USE_DIV = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_FAMILY = virtex5
PARAMETER C_INSTANCE = microblaze_0
PARAMETER C_FSL_LINKS = 1
PARAMETER C_PVR = 2
PARAMETER C_CACHE_BYTE_SIZE = 2048
PARAMETER C_DCACHE_BYTE_SIZE = 4096
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE ixcl = ixcl
BUS_INTERFACE dxcl = dxcl
BUS_INTERFACE DEBUG = microblaze_0_dbg
BUS_INTERFACE SFSL0 = download_link
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
PORT RESET = mb_reset
PORT Interrupt = Interrupt
END

BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.00.a
PARAMETER C_ADDR_PIPELINING_TYPE = 1
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_DTE
PARAMETER HW_VER = 1.00.a
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = RS232_DTE_Interrupt
PORT RX = fpga_0_RS232_DTE_RX
PORT TX = fpga_0_RS232_DTE_TX
END

BEGIN xps_timer
PARAMETER INSTANCE = xps_timer_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x41C00000
PARAMETER C_HIGHADDR = 0x41C0FFFF
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = xps_timer_1_Interrupt
END

BEGIN xps_mch_emc
PARAMETER INSTANCE = FLASH
PARAMETER HW_VER = 1.00.a
PARAMETER C_NUM_CHANNELS = 0
PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_MAX_MEM_WIDTH = 8
PARAMETER C_MEM0_WIDTH = 8
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_TCEDV_PS_MEM_0 = 110000
PARAMETER C_TWC_PS_MEM_0 = 110000
PARAMETER C_TAVDV_PS_MEM_0 = 110000
PARAMETER C_TWP_PS_MEM_0 = 70000
PARAMETER C_THZCE_PS_MEM_0 = 35000
PARAMETER C_TLZWE_PS_MEM_0 = 15000
PARAMETER C_MEM0_BASEADDR = 0x89000000
PARAMETER C_MEM0_HIGHADDR = 0x89ffffff
BUS_INTERFACE SPLB = mb_plb
PORT Mem_A = fpga_0_FLASH_Mem_A_split
PORT Mem_DQ = fpga_0_FLASH_Mem_DQ
PORT Mem_OEN = fpga_0_FLASH_Mem_OEN
PORT Mem_WEN = fpga_0_FLASH_Mem_WEN
PORT Mem_CEN = fpga_0_FLASH_Mem_CEN
PORT Mem_ADV_LDN = FLASH_Mem_ADV_LDN
END

BEGIN util_bus_split
PARAMETER INSTANCE = FLASH_util_bus_split_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 0
PARAMETER C_SPLIT = 8
PORT Sig = fpga_0_FLASH_Mem_A_split
PORT Out2 = fpga_0_FLASH_Mem_A
END

BEGIN mpmc
PARAMETER INSTANCE = DDR2_SDRAM
PARAMETER HW_VER = 3.00.a
PARAMETER C_NUM_PORTS = 4
PARAMETER C_PIM0_BASETYPE = 1
PARAMETER C_PIM1_BASETYPE = 1
PARAMETER C_MEM_PARTNO = mt4htf3264h-53e
PARAMETER C_NUM_IDELAYCTRL = 3
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y5-IDELAYCTRL_X0Y1-IDELAYCTRL_X0Y0
PARAMETER C_MEM_CE_WIDTH = 2
PARAMETER C_MEM_CS_N_WIDTH = 2
PARAMETER C_MEM_CLK_WIDTH = 2
PARAMETER C_MEM_ODT_WIDTH = 2
PARAMETER C_MEM_ODT_TYPE = 1
PARAMETER C_XCL0_WRITEXFER = 0
PARAMETER C_PIM2_BASETYPE = 2
PARAMETER C_PIM3_BASETYPE = 3
PARAMETER C_MPMC_CLK0_PERIOD_PS = 8000
PARAMETER C_SDMA3_PI2LL_CLK_RATIO = 1
PARAMETER C_MPMC_BASEADDR = 0x20000000
PARAMETER C_MPMC_HIGHADDR = 0x2FFFFFFF
PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460FFFF
BUS_INTERFACE XCL0 = ixcl
BUS_INTERFACE XCL1 = dxcl
BUS_INTERFACE SPLB2 = mb_plb
BUS_INTERFACE SDMA_CTRL3 = mb_plb
PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT
PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DDR2_Addr
PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DDR2_BankAddr
PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DDR2_CAS_n
PORT DDR2_CE = fpga_0_DDR2_SDRAM_DDR2_CE
PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DDR2_WE_n
PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DDR2_Clk
PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM
PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS
# PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n
PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ
PORT MPMC_Clk0 = sys_clk_s
PORT MPMC_Clk90 = DDR2_SDRAM_mpmc_clk_90_s
PORT SDMA3_Clk = sys_clk_s
PORT MPMC_Clk_200MHz = clk_200mhz_s
PORT MPMC_Rst = sys_bus_reset
PORT SDMA3_Rx_IntOut = DDR2_SDRAM_SDMA3_Rx_IntOut
PORT SDMA3_Tx_IntOut = DDR2_SDRAM_SDMA3_Tx_IntOut
PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DDR2_Clk_n
PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DDR2_RAS_n
PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DDR2_CS_n
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 125000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = GROUP0
PARAMETER C_CLKOUT2_FREQ = 125000000
PARAMETER C_CLKOUT2_PHASE = 90
PARAMETER C_CLKOUT2_GROUP = GROUP0
PARAMETER C_CLKOUT3_FREQ = 62500000
PARAMETER C_CLKOUT3_PHASE = 0
PARAMETER C_CLKOUT3_GROUP = NONE
PARAMETER C_CLKOUT4_FREQ = 200000000
PARAMETER C_CLKOUT4_PHASE = 0
PARAMETER C_CLKOUT4_GROUP = NONE
PORT CLKOUT0 = sys_clk_s
PORT CLKOUT2 = DDR2_SDRAM_mpmc_clk_90_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
PORT CLKOUT3 = DDR2_SDRAM_MPMC_Clk_Div2
PORT CLKOUT4 = clk_200mhz_s
END

BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
PARAMETER C_WRITE_FSL_PORTS = 1
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
BUS_INTERFACE MFSL0 = download_link
PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
END

BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120FFFF
BUS_INTERFACE SPLB = mb_plb
PORT Irq = Interrupt
PORT Intr = xps_timer_1_Interrupt&RS232_DTE_Interrupt&DDR2_SDRAM_SDMA3_Rx_IntOut&DDR2_SDRAM_SDMA3_Tx_IntOut
END

BEGIN fsl_v20
PARAMETER INSTANCE = download_link
PARAMETER HW_VER = 2.11.a
PORT SYS_Rst = sys_bus_reset
PORT FSL_Clk = sys_clk_s
END

MSS FILE:
--------------------------------------------------------------
PARAMETER VERSION = 2.2.0

BEGIN OS
PARAMETER OS_NAME = petalinux
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER lmb_memory = dlmb_cntlr
PARAMETER stdin = RS232_DTE
PARAMETER stdout = RS232_DTE
PARAMETER main_memory = DDR2_SDRAM
PARAMETER main_memory_bank = 0
PARAMETER flash_memory_bank = 0
END

# PARAMETER microblaze_exception_vectors = ((XEXC_NONE,default,1))
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.11.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER CORE_CLOCK_FREQ_HZ = 125000000
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = lmb_bram
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.12.a
PARAMETER HW_INSTANCE = RS232_DTE
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = mpmc
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = DDR2_SDRAM
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = clock_generator_0
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.12.a
PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = proc_sys_reset_0
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 1.10.b
PARAMETER HW_INSTANCE = xps_timer_1
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.10.c
PARAMETER HW_INSTANCE = xps_intc_0
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = emc
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = FLASH
END

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