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[microblaze-uclinux] MMU build crashes on boot (Virtex4, MicroBlaze 7.20.c, ISE/EDK 11.3)
Hi all,
I'm debugging a crash of a freshly built MMU kernel on a custom Virtex-4
board (that looks a lot like the ML402.) Both Linus' kernel.org git
tree, and the Xilinx tree, exhibit the same behaviour. The __log_buf was
retrieved using xmd. Here are the contents:
<5>Linux version 2.6.31-12324-gb6e0eb9-dirty (gsmecher@tonka) (gcc
version 4.1.2) #10 Thu Nov 12 08:17:13 PST 2009
<6>setup_cpuinfo: initialising
<4>setup_cpuinfo: No PVR support. Using static CPU info from FDT
<6>setup_memory: max_mapnr: 0x4000
<6>setup_memory: min_low_pfn: 0x44000
<6>setup_memory: max_low_pfn: 0x48000
<7>On node 0 totalpages: 16384
<7>free_area_init_node: node 0, pgdat c034d2e4, node_mem_map c046b000
<7> Normal zone: 128 pages used for memmap
<7> Normal zone: 0 pages reserved
<7> Normal zone: 16256 pages, LIFO batch:3
<4>Built 1 zonelists in Zone order, mobility grouping on. Total
pages: 16256
<5>Kernel command line: console=TTYUL0
<4>PID hash table entries: 256 (order: 8, 1024 bytes)
<6>Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
<6>Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
<6>Memory: 60316k/65536k available
<6>NR_IRQS:32
<4>Oops: kernel access of bad area, sig: 11
<6> Registers dump: mode=1\r
<6> r1=C0351FAC, r2=C033BB00, r3=00000000, r4=00000000
<6> r5=C0348190, r6=C02CECCC, r7=FFFFFFF6, r8=00000003
<6> r9=00000041, r10=C034D2E4, r11=00003AE1, r12=8000003E
<6> r13=C0352000, r14=C0009910, r15=C0356220, r16=00000000
<6> r17=00000000, r18=00000000, r19=C3FFFDEC, r20=00000000
<6> r21=00000000, r22=00000000, r23=C029F760, r24=00000000
<6> r25=00000000, r26=00000000, r27=00000000, r28=00000000
<6> r29=00000000, r30=00000000, r31=C033E2C8, rPC=C0356230
<6> msr=000041AA, ear=00000000, esr=00000B12, fsr=00000000
<0>Kernel panic - not syncing: Attempted to kill the idle task!
<0>Rebooting in 120 seconds..
<5>Machine restart...
<6>
<6>Stack:
<6> c0351d38 c02a2e34 c0351f14 c0350000 c0351d54 c0028108 c02a05c8
00000199
<4> 00000000 00000000 19981fc0 00000000 c00155dc c033e2c8 00000000
00000000
<4> c0351f14 00000034 c033e2c8 c0019e78 c02a2ac0 00000078 c043c944
ffffffff
<5>Call Trace:
<5>
<4>[<c0028108>] emergency_restart+0xc/0x20
<4>[<c00155dc>] panic+0x158/0x210
<4>[<c0019e78>] do_exit+0x6a8/0x734
<4>[<c0000968>] die+0x88/0x90
<4>[<c0009bac>] bad_page_fault+0x58/0x64
<4>[<c0009d38>] do_page_fault+0x180/0x504
<4>[<c0073b4c>] cache_alloc_refill+0x1c0/0xa8c
<4>[<c005175c>] __alloc_pages_nodemask+0x144/0x624
<4>[<c00084a8>] page_fault_instr_trap+0x1f8/0x200
<4>[<c0072638>] cache_alloc_debugcheck_after+0x194/0x1ec
<4>[<c0051c4c>] __get_free_pages+0x10/0x94
<4>[<c006e0a0>] alloc_vmap_area+0x68/0x360
<4>[<c006e248>] alloc_vmap_area+0x210/0x360
<4>[<c006e420>] __get_vm_area_node+0x88/0x37c
<4>[<c006e440>] __get_vm_area_node+0xa8/0x37c
<4>[<c02986b0>] _spin_lock+0xc/0x20
<4>[<c00611c8>] __pte_alloc_kernel+0x88/0xec
<4>[<c0352000>] _esbss+0x0/0x14
<4>[<c0009910>] ioremap+0x80/0x148
<4>[<c0356220>] init_IRQ+0xe0/0x294
<4>[<c0356230>] init_IRQ+0xf0/0x294
<4>[<c03528f8>] start_kernel+0x240/0x4d4
<4>[<c0004a00>] machine_halt+0x0/0x20
Early printk also had something to say on the serial port:
early_printk_console is enabled at 0x84000000
Ramdisk addr 0x0000000a, Compiled-in FDT at 0x4423ad0c
The MHS file follows:
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX_pin, DIR = I
PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =
fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =
fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =
fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =
fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =
fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =
fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =
fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin,
DIR = O
PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin =
fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin,
DIR = O
PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin =
fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin =
fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin,
DIR = O
PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =
fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin,
DIR = O, VEC = [12:0]
PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR
= IO, VEC = [31:0]
PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR
= O, VEC = [3:0]
PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin,
DIR = IO, VEC = [3:0]
PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin =
fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin =
fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_crs_pin =
fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_dv_pin =
fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin =
fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0]
PORT fpga_0_Ethernet_MAC_PHY_col_pin =
fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin =
fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin =
fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O
PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin =
fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O
PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin =
fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0]
PORT fpga_0_Ethernet_MAC_PHY_MDC_pin =
fpga_0_Ethernet_MAC_PHY_MDC_pin, DIR = O
PORT fpga_0_Ethernet_MAC_PHY_MDIO_pin =
fpga_0_Ethernet_MAC_PHY_MDIO_pin, DIR = IO
PORT fpga_0_Ethernet_MAC_PHY_INTR_pin =
fpga_0_Ethernet_MAC_PHY_INTR_pin, DIR = I, SIGIS = INTERRUPT,
SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK,
CLK_FREQ = 25000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST,
RST_POLARITY = 0
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0x44000000
PARAMETER C_ICACHE_HIGHADDR = 0x47ffffff
PARAMETER C_CACHE_BYTE_SIZE = 16384
PARAMETER C_ICACHE_ALWAYS_USED = 1
PARAMETER C_DCACHE_BASEADDR = 0x44000000
PARAMETER C_DCACHE_HIGHADDR = 0x47ffffff
PARAMETER C_DCACHE_BYTE_SIZE = 16384
PARAMETER C_DCACHE_ALWAYS_USED = 1
PARAMETER HW_VER = 7.20.c
PARAMETER C_USE_ICACHE = 1
PARAMETER C_USE_DCACHE = 1
PARAMETER C_USE_MMU = 3
PARAMETER C_MMU_ZONES = 2
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DXCL = microblaze_0_DXCL
BUS_INTERFACE IXCL = microblaze_0_IXCL
BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
PORT MB_RESET = mb_reset
PORT INTERRUPT = microblaze_0_Interrupt
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.04.a
PORT PLB_Clk = clk_100_0000MHzDCM0
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = clk_100_0000MHzDCM0
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = clk_100_0000MHzDCM0
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_Uart
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER HW_VER = 1.01.a
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_Uart_RX_pin
PORT TX = fpga_0_RS232_Uart_TX_pin
PORT Interrupt = xps_RS232_0_Interrupt
END
BEGIN xps_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER C_MEM_WIDTH = 16
PARAMETER HW_VER = 1.01.a
PARAMETER C_BASEADDR = 0x83600000
PARAMETER C_HIGHADDR = 0x8360ffff
BUS_INTERFACE SPLB = mb_plb
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
PORT SysACE_CLK = dcm_clk_s
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
END
BEGIN mpmc
PARAMETER INSTANCE = DDR_SDRAM
PARAMETER C_NUM_PORTS = 2
PARAMETER C_NUM_IDELAYCTRL = 1
PARAMETER C_IDELAYCTRL_LOC = NOT_SET
# PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y4-IDELAYCTRL_X0Y5
PARAMETER C_MEM_TYPE = DDR
PARAMETER C_MEM_PARTNO = MT46V16M16-6T
PARAMETER C_MEM_DATA_WIDTH = 32
PARAMETER C_MEM_DM_WIDTH = 4
PARAMETER C_MEM_DQS_WIDTH = 4
PARAMETER C_PIM0_BASETYPE = 1
PARAMETER C_PIM1_BASETYPE = 1
PARAMETER HW_VER = 5.03.a
PARAMETER C_MPMC_BASEADDR = 0x44000000
PARAMETER C_MPMC_HIGHADDR = 0x47ffffff
BUS_INTERFACE XCL0 = microblaze_0_IXCL
BUS_INTERFACE XCL1 = microblaze_0_DXCL
PORT MPMC_Clk0 = clk_100_0000MHzDCM0
PORT MPMC_Clk90 = clk_100_0000MHz90DCM0
PORT MPMC_Clk_200MHz = clk_200_0000MHz
PORT MPMC_Rst = sys_periph_reset
PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin
PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin
PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin
PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin
PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin
PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin
PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin
PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin
PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin
PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin
PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin
END
BEGIN xps_ethernetlite
PARAMETER INSTANCE = Ethernet_MAC
PARAMETER HW_VER = 3.01.a
PARAMETER C_BASEADDR = 0x81000000
PARAMETER C_HIGHADDR = 0x8100ffff
BUS_INTERFACE SPLB = mb_plb
PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin
PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin
PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin
PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin
PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin
PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin
PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin
PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin
PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin
PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin
PORT PHY_MDC = fpga_0_Ethernet_MAC_PHY_MDC_pin
PORT PHY_MDIO = fpga_0_Ethernet_MAC_PHY_MDIO_pin
END
BEGIN xps_timer
PARAMETER INSTANCE = xps_timer_0
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 0
PARAMETER HW_VER = 1.01.b
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = xps_timer_0_Interrupt
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_CLKIN_FREQ = 25000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_PHASE = 90
PARAMETER C_CLKOUT0_GROUP = DCM0
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT1_FREQ = 100000000
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = DCM0
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT2_FREQ = 200000000
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = NONE
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER HW_VER = 3.01.a
PORT CLKIN = dcm_clk_s
PORT CLKOUT0 = clk_100_0000MHz90DCM0
PORT CLKOUT1 = clk_100_0000MHzDCM0
PORT CLKOUT2 = clk_200_0000MHz
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END
BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER HW_VER = 1.00.f
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 2.00.a
PORT Slowest_sync_clk = clk_100_0000MHzDCM0
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END
BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = mb_plb
PORT Intr = xps_timer_0_Interrupt &
fpga_0_Ethernet_MAC_PHY_INTR_pin & xps_RS232_0_Interrupt
PORT Irq = microblaze_0_Interrupt
END
Here is my .dts file:
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,microblaze";
model = "testing";
DDR_SDRAM: memory@44000000 {
device_type = "memory";
reg = < 0x44000000 0x4000000 >;
} ;
alias {
ethernet0 = &Ethernet_MAC;
serial0 = &RS232_Uart;
} ;
chosen {
bootargs = "console=TTYUL0";
} ;
cpus {
#address-cells = <1>;
#cpus = <0x1>;
#size-cells = <0>;
microblaze_0: cpu@0 {
clock-frequency = <100000000>;
compatible = "xlnx,microblaze-7.20.c";
d-cache-line-size = <0x10>;
d-cache-size = <0x4000>;
device_type = "cpu";
i-cache-line-size = <0x10>;
i-cache-size = <0x4000>;
model = "microblaze,7.20.c";
reg = <0>;
timebase-frequency = <100000000>;
xlnx,addr-tag-bits = <0xc>;
xlnx,allow-dcache-wr = <0x1>;
xlnx,allow-icache-wr = <0x1>;
xlnx,area-optimized = <0x0>;
xlnx,cache-byte-size = <0x4000>;
xlnx,d-lmb = <0x1>;
xlnx,d-opb = <0x0>;
xlnx,d-plb = <0x1>;
xlnx,data-size = <0x20>;
xlnx,dcache-addr-tag = <0xc>;
xlnx,dcache-always-used = <0x1>;
xlnx,dcache-byte-size = <0x4000>;
xlnx,dcache-interface = <0x0>;
xlnx,dcache-line-len = <0x4>;
xlnx,dcache-use-fsl = <0x1>;
xlnx,dcache-use-writeback = <0x0>;
xlnx,debug-enabled = <0x1>;
xlnx,div-zero-exception = <0x0>;
xlnx,dopb-bus-exception = <0x0>;
xlnx,dynamic-bus-sizing = <0x1>;
xlnx,edge-is-positive = <0x1>;
xlnx,family = "virtex4";
xlnx,fpu-exception = <0x0>;
xlnx,fsl-data-size = <0x20>;
xlnx,fsl-exception = <0x0>;
xlnx,fsl-links = <0x0>;
xlnx,i-lmb = <0x1>;
xlnx,i-opb = <0x0>;
xlnx,i-plb = <0x1>;
xlnx,icache-always-used = <0x1>;
xlnx,icache-interface = <0x0>;
xlnx,icache-line-len = <0x4>;
xlnx,icache-use-fsl = <0x1>;
xlnx,ill-opcode-exception = <0x0>;
xlnx,instance = "microblaze_0";
xlnx,interconnect = <0x1>;
xlnx,interrupt-is-edge = <0x0>;
xlnx,iopb-bus-exception = <0x0>;
xlnx,mmu-dtlb-size = <0x4>;
xlnx,mmu-itlb-size = <0x2>;
xlnx,mmu-tlb-access = <0x3>;
xlnx,mmu-zones = <0x2>;
xlnx,number-of-pc-brk = <0x1>;
xlnx,number-of-rd-addr-brk = <0x0>;
xlnx,number-of-wr-addr-brk = <0x0>;
xlnx,opcode-0x0-illegal = <0x0>;
xlnx,pvr = <0x0>;
xlnx,pvr-user1 = <0x0>;
xlnx,pvr-user2 = <0x0>;
xlnx,reset-msr = <0x0>;
xlnx,sco = <0x0>;
xlnx,unaligned-exceptions = <0x0>;
xlnx,use-barrel = <0x0>;
xlnx,use-dcache = <0x1>;
xlnx,use-div = <0x0>;
xlnx,use-ext-brk = <0x1>;
xlnx,use-ext-nm-brk = <0x1>;
xlnx,use-extended-fsl-instr = <0x0>;
xlnx,use-fpu = <0x0>;
xlnx,use-hw-mul = <0x1>;
xlnx,use-icache = <0x1>;
xlnx,use-interrupt = <0x1>;
xlnx,use-mmu = <0x3>;
xlnx,use-msr-instr = <0x1>;
xlnx,use-pcmp-instr = <0x1>;
} ;
} ;
mb_plb: plb@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,plb-v46-1.04.a", "xlnx,plb-v46-1.00.a",
"simple-bus";
ranges ;
Ethernet_MAC: ethernet@81000000 {
compatible = "xlnx,xps-ethernetlite-3.01.a";
device_type = "network";
local-mac-address = [ 02 00 00 00 00 00 ];
reg = < 0x81000000 0x10000 >;
xlnx,duplex = <0x1>;
xlnx,family = "virtex4";
xlnx,include-internal-loopback = <0x0>;
xlnx,include-mdio = <0x1>;
xlnx,rx-ping-pong = <0x0>;
xlnx,tx-ping-pong = <0x0>;
} ;
RS232_Uart: serial@84000000 {
clock-frequency = <100000000>;
compatible = "xlnx,xps-uartlite-1.01.a",
"xlnx,xps-uartlite-1.00.a";
current-speed = <115200>;
device_type = "serial";
interrupt-parent = <&xps_intc_0>;
interrupts = < 0 0 >;
port-number = <0>;
reg = < 0x84000000 0x10000 >;
xlnx,baudrate = <0x1c200>;
xlnx,data-bits = <0x8>;
xlnx,family = "virtex4";
xlnx,odd-parity = <0x0>;
xlnx,use-parity = <0x0>;
} ;
SysACE_CompactFlash: sysace@83600000 {
compatible = "xlnx,xps-sysace-1.01.a",
"xlnx,xps-sysace-1.00.a";
reg = < 0x83600000 0x10000 >;
xlnx,family = "virtex4";
xlnx,mem-width = <0x10>;
} ;
mdm_0: debug@84400000 {
compatible = "xlnx,mdm-1.00.f";
reg = < 0x84400000 0x10000 >;
xlnx,family = "virtex4";
xlnx,interconnect = <0x1>;
xlnx,jtag-chain = <0x2>;
xlnx,mb-dbg-ports = <0x1>;
xlnx,uart-width = <0x8>;
xlnx,use-uart = <0x1>;
xlnx,write-fsl-ports = <0x0>;
} ;
xps_intc_0: interrupt-controller@81800000 {
#interrupt-cells = <0x2>;
compatible = "xlnx,xps-intc-2.00.a", "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = < 0x81800000 0x10000 >;
xlnx,num-intr-inputs = <0x3>;
} ;
xps_timer_0: timer@83c00000 {
compatible = "xlnx,xps-timer-1.01.b";
interrupt-parent = <&xps_intc_0>;
interrupts = < 2 2 >;
reg = < 0x83c00000 0x10000 >;
xlnx,count-width = <0x20>;
xlnx,family = "virtex4";
xlnx,gen0-assert = <0x1>;
xlnx,gen1-assert = <0x1>;
xlnx,one-timer-only = <0x0>;
xlnx,trig0-assert = <0x1>;
xlnx,trig1-assert = <0x1>;
} ;
} ;
} ;
Any ideas? It looks (to my untrained eye) like the MMU is incorrectly
configured. This is using Microblaze 7.20.c, which the Xilinx wikidot
page claims has known cache errors. I realize the kernel and toolchain
are currently in flux, but I'm interested in getting a build up and
running so I can keep developing while things to settle down. Please let
me know if you need any more information.
thanks,
Graeme
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