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Re: [partial-reconfig] Inter-module Communication
Tyrone Kwok wrote:
> Hi all,
>
> Suppose that in my design, there are three parts in the FPGA:
>
> |A | B | C |
>
> and that B is a reconfigurable moudle while A and C are static.
>
> My question is how inter-moudle communication is done in the
> following situations:
>
> 1. C needs to use some I/O pins in A, and the I/O signals
> can't be interrupted after the system starts.
>
> 2. C needs to use some I/O pins in B, and the I/O signals
> can't be interrupted after the system starts.
>
> For situation 1, I think the commuication can be done using
> bus macros, right ?
Exactly, but you need to create your own macros to span the area of
module B in FPGA Editor. In my experience this (i.e. the crossing of
modules via bus macros) is something the tools have a lot of problems
with. It seems to help if you make the macros wider, i.e. don't let them
end directly at the module borders, but several CLB columns inside the
modules. I have no idea why that is, or if that can be considered a real
solution, but it has helped in my case.
> For situation 2, I have no idea on how to main the connection
> while B is being reconfigured.
You could create a bus macro, and wire it's in/outputs to the IOBs
manually in FPGA Editor. In theory that should be possible, but I
haven't tried this so far.
With ISE5.2 you can place a regular bus macro at the border between C
and B, and connect the macro ports that reside in B with the IOBs in the
top-level design (ISE6.1 usually gives you an error "Due to existing
islands"). Most of the time (but not always), par will route those
top-level-nets in the same way (so they will stay intact during
reconfiguration), unless the routing ressources are used up otherwise.
But I'm afraid there is no really "safe" way to do this...
--
Best regards,
Sean Durkin
Fraunhofer Institute for Integrated Circuits IIS
Dep. Electronic Imaging - HIS (Bildsensorik - HIS)
Am Wolfsmantel 33
91058 Erlangen
Germany
Fon: +49 9131 776 503
Fax: +49 9131 776 598
Web: http://www.iis.fraunhofer.de
mailto:durkinsn@iis.fraunhofer.de
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