[partial-reconfig] partial-reconfig: Bus macro problem

["Jens Thorvinger" <jthorv@xxxxxxx>]

Suppose that in my design, there are three parts in the FPGA:

  | A | B | C |

and that B is a reconfigurable moudle while A and C are static.

Communication between the are done through the bus macro provided by Xilinx. No problem.

In order to have a communication between A and C while B is reconfigured I need a wider static hard macro going from A to C. I need to create my own macro and to test this I first tried to create a macro identical to the one by Xilinx. Just to make sure this works.

The one I build is however not routed properly into the design. I can write to my bus but I cannot read from it. My macro is visibly exactly the same as the Xilinx macro (looking at it in FPGA_Editor). BUT, the result is that the signals reading the bus are not routed onto it when routed as a reconfigrable module. In the final routing when the entire structure is routed it does the routing right or it violates the DISALLOW_BOUNDARY_CROSSING constraint but still manage to rout it. It is however in either way useless as reconfigurabel module.

Could you please help me out?

regards
/Jens



___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/