Re: [partial-reconfig] partial-reconfig: Bus macro problem

[Sean Durkin <durkinsn@xxxxxxxxxxxxxxxxx>]

Jens Thorvinger wrote:

> Suppose that in my design, there are three parts in the FPGA:
> 
>   | A | B | C |
> 
> and that B is a reconfigurable moudle while A and C are static.
> 
> Communication between the are done through the bus macro provided by Xilinx. No problem.
> 
> In order to have a communication between A and C while B is reconfigured I need a wider static hard macro going from A to C. I need to create my own macro and to test this I first tried to create a macro identical to the one by Xilinx. Just to make sure this works.
> 
> The one I build is however not routed properly into the design. I can write to my bus but I cannot read from it. My macro is visibly exactly the same as the Xilinx macro (looking at it in FPGA_Editor). BUT, the result is that the signals reading the bus are not routed onto it when routed as a reconfigrable module. In the final routing when the entire structure is routed it does the routing right or it violates the DISALLOW_BOUNDARY_CROSSING constraint but still manage to rout it. It is however in either way useless as reconfigurabel module.
> 
> Could you please help me out?
Try the following at the command prompt:

xdl -ncd2xdl macro_filename.nmc

This converts the bus macro to an XDL-description. Have a look at the 
.XDL-file this generates. For each net, there should be a section where 
it specifies which PIPs to use and such. For each net there should be an 
attribute like this:

   cfg "_NET_PROP::IS_BUS_MACRO:" ,

FPGA Editor usually "forgets" to put that in.
In case this attribute is not set for your bus macro, it could help to 
insert it manually in the .XDL-file and convert that back to ncd-format:

xdl -xdl2ncd bm_v2p_4b.xdl

This gives you an .ncd-file which you have to rename to .nmc to be able 
to use it as a macro.

Don't know if this will help you, but I always had to manually insert 
the above attribute for all nets in the macros I did myself in FPGA 
Editor, since FPGA Editor never does it...

BTW, I'm not sure if all of this works satisfactory with ISE6.1/6.2... 
When using XDL in ISE6, I always get a warning that "this is a new 
revision ncd, some features might be lost", so haven't thoroughly tested 
that.

-- 
Best regards,

Sean Durkin
Fraunhofer Institute for Integrated Circuits IIS
Dep. Electronic Imaging - HIS (Bildsensorik - HIS)
Am Wolfsmantel 33
91058 Erlangen
Germany

Fon: +49 9131 776 503
Fax: +49 9131 776 598

Web: http://www.iis.fraunhofer.de
mailto:durkinsn@iis.fraunhofer.de
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