Re: [partial-reconfig] partial-reconfig: Bus macro problem

[<jedward@xxxxxxxxxx>]

     I have a doubt about this problem. If I use a hard bus macro to
     communicate static modules A and C, while B is reconfiguring. How can
     i be sure that a hard bus macro inside module B is not part of
     reconfiguration frame?. Is it possivel? or always that I remove the
     module B, a hard bus macro across the module B is removed too?
     Thanks.

 John Edward Esquiagola Aranda
 Laboratorio de Microeletrônica
 Escola Politecnica da Universidade de São Paulo

> Jens Thorvinger wrote:
>
>> The one I build is however not routed properly into the design. I can
>> write to my bus but I cannot read from it. My macro is visibly
>> exactly the same as the Xilinx macro (looking at it in FPGA_Editor).
>> BUT, the result is that the signals reading the bus are not routed
>> onto it when routed as a reconfigrable module. In the final routing
>> when the entire structure is routed it does the routing right or it
>> violates the DISALLOW_BOUNDARY_CROSSING constraint but still manage to
>> rout it. It is however in either way useless as reconfigurabel module.
>>
>> Could you please help me out?
> Maybe this could help you, too (posted to comp.arch.fpga by Amaury
> Anciaux, who had a similar problem as you did). I suggested to him the
> same thing I did to you (i.e. check for the attributes with XDL), here
> is what he replied:
>
> "The bus macro doesn't seem to lack anything, but I discovered that if
> I route the concerned signal to a "pip" further to the left, the design
> finally routes. So it seems that the PAR needs to have that first part
> of the path to route the signal."
>
> --
> Best regards,
>
> Sean Durkin
> Fraunhofer Institute for Integrated Circuits IIS
> Dep. Electronic Imaging - HIS (Bildsensorik - HIS)
> Am Wolfsmantel 33
> 91058 Erlangen
> Germany
>
> Fon: +49 9131 776 503
> Fax: +49 9131 776 598
>
> Web: http://www.iis.fraunhofer.de
> mailto:durkinsn@iis.fraunhofer.de
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