[partial-reconfig] Handling open outputs of bus macros

["Tyrone Kwok" <tokwok@xxxxxxxxxxx>]

Hi all,

I was told that open signals of bus macros need to be handled by using
patch signals as follows:

signal input_connect : std_logic;   -- connect to output of bus macro
signal input_patch : std_logic;

patcher: process(clk, input_connect)
begin
   if (clk'event and clk = '1') then
      input_patch <= input_connect;
  end if;
end process patcher;

I've explicitly told the synthesis tool to keep the above signals and I've
checked that it does keep the signals. However, during mapping and
PAR, there are warning messages saying that no load for the output
of the bus macro (during ngdbuild, there's no such warning). I then checked
it in FPGA Editor and found that there is no signal connecting to the 
output.
I would like to ask why this happens and how to handle it ?

Many thanks !!!

tk

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